Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers

Abstract

Three-dimensional (3D) integration schemes of fabricating a 3D integrated circuit in which the pFETs are located on an optimal crystallographic surface for that device and the nFETs are located on a optimal crystallographic surface for that type of device are provided. In accordance with a first 3D integration scheme of the present invention, first semiconductor devices are pre-built on a semiconductor surface of a first silicon-on-insulator (SOI) substrate and second semiconductor devices are pre-built on a semiconductor surface of a second SOI substrate. After pre-building those two structures, the structure are bonded together and interconnect through wafer-via through vias. In a second 3D integration scheme, a blanket silicon-on-insulator (SOI) substrate having a first SOI layer of a first crystallographic orientation is bonded to a surface of a pre-fabricating wafer having second semiconductor devices on a second SOI layer that has a different crystallographic orientation than the first SOI layer; and forming first semiconductor device on the first SOI layer.

Description

Technical field [0001] The present invention relates to a complementary metal oxide semiconductor (CMOS) integrated circuit, and more specifically to a three-dimensional CMOS integrated circuit with semiconductor device layers fabricated on wafers with different crystal orientations. Background technique [0002] In current semiconductor technology, CMOS devices such as nFET or pFET are typically manufactured on a semiconductor wafer having a single crystal orientation such as silicon. In particular, most of today's semiconductor devices are fabricated on silicon with (100) crystal orientation. [0003] It is known that electrons have high mobility in the (100) silicon surface orientation, but holes have high mobility in the (110) surface orientation. That is, the hole mobility on (100) silicon is about 2-4 times lower than the corresponding electron mobility in this crystal orientation. In order to compensate for this difference, pFETs are usually designed to have a larger width...

AI Technical Summary

Problems solved by technology

Circuits fabricated in this way suffer from two major disadvantages: (1) the recrystallized top layer often has poor electrical properties, which may lead to lower device and circuit performance; it is also difficult to control the surface orientation of the recrystallized layer; (2) Thermal cycling from top layer formation to subsequent device fabrication degrades underlying device performance

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