Multi-chip three-dimensional packaging structure and packaging method

Abstract

The invention belongs to the technical field of chip packaging, and particularly relates to a multi-chip three-dimensional packaging structure and packaging method.The packaging method comprises the following steps that a carrier plate is provided, a preset circuit is manufactured on one side face in the thickness direction of the carrier plate, and the preset circuit is electrically led out towards the edge of the carrier plate; a plurality of elements are provided, the elements are one or more of chips, wafers, cooling fins or functional areas, and ports of the chips, the wafers and the functional areas are arranged on respective edges of the chips, the wafers and the functional areas; the method comprises the following steps: spatially overturning a plurality of elements in a vacuum environment to form a cubic structure, and hermetically connecting the edges of the cubic structure through an adhesive; connecting the port of the preset circuit of the carrier plate with the ports of the plurality of elements through a flexible conductive wire rod in a bonding manner; and wrapping the outer surface of the cubic structure with a plastic package material to form a plastic package layer. According to the invention, the interconnection among a plurality of chips is realized through the flexible conductive wire rod, the length of the interconnection wire can be obviously shortened, the influence on signal transmission is reduced, and the performance of the chip is improved.

Description

technical field [0001] The invention belongs to the technical field of chip packaging, and in particular relates to a multi-chip three-dimensional packaging structure and packaging method. Background technique [0002] At present, most integrated circuits adopt the form of planar packaging, that is, the packaging technology of integrating a single chip in the same plane. Due to the limitation of area, it is difficult to integrate multiple chips on the same plane. The so-called three-dimensional packaging is an emerging integrated circuit packaging technology in recent years, which breaks through the traditional concept of planar packaging. It is a package in which multiple chips are stacked in a single package in a three-dimensional space to package chips or bare chips. technology. However, the existing three-dimensional packaging technology basically adopts a "stacking + vertical conduction" packaging method for multiple chips. This packaging structure has the disadvantag...

AI Technical Summary

Problems solved by technology

However, the existing three-dimensional packaging technology basically adopts the packaging method of "stacking + vertical conduction" for multiple chips. This packaging structure has the disadvantages of scattered and complicated lines and too long conductive lines.

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