Multi-chip three-dimensional packaging structure and packaging method

An encapsulation method and encapsulation structure technology, which can be applied in the manufacture of electrical solid devices, semiconductor devices, and semiconductor/solid state devices, etc., can solve the problems of excessively long conductive lines, scattered lines, and complexity, and shorten the lead length, reduce the difficulty of packaging, The effect of simplifying the packaging process

Pending Publication Date: 2022-03-01
广东佛智芯微电子技术研究有限公司 +1
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Problems solved by technology

However, the existing three-dimensional packaging technology basically adopts the packaging method of "stacking + vertical conduction

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  • Multi-chip three-dimensional packaging structure and packaging method
  • Multi-chip three-dimensional packaging structure and packaging method
  • Multi-chip three-dimensional packaging structure and packaging method

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[0035] Next, the technical solutions in the embodiments of the present invention will be apparent from the embodiments of the present invention, and embodiments are merely described, as described in the embodiments of the invention, not all of the embodiments of the present invention. Components of the embodiments of the present invention described and illustrated in the drawings herein can be arranged and design in various configurations. Thus, the following detailed description of the embodiments of the invention in the drawings is not intended to limit the scope of the invention claims, but only the selected embodiments of the present invention are shown. Based on the embodiments of the present invention, those skilled in the art will belong to the scope of the present invention without making creative labor.

[0036] It should be noted that similar reference numerals and letters represent the similar items in the following figures, and therefore, once one is defined in one bys...

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Abstract

The invention belongs to the technical field of chip packaging, and particularly relates to a multi-chip three-dimensional packaging structure and packaging method.The packaging method comprises the following steps that a carrier plate is provided, a preset circuit is manufactured on one side face in the thickness direction of the carrier plate, and the preset circuit is electrically led out towards the edge of the carrier plate; a plurality of elements are provided, the elements are one or more of chips, wafers, cooling fins or functional areas, and ports of the chips, the wafers and the functional areas are arranged on respective edges of the chips, the wafers and the functional areas; the method comprises the following steps: spatially overturning a plurality of elements in a vacuum environment to form a cubic structure, and hermetically connecting the edges of the cubic structure through an adhesive; connecting the port of the preset circuit of the carrier plate with the ports of the plurality of elements through a flexible conductive wire rod in a bonding manner; and wrapping the outer surface of the cubic structure with a plastic package material to form a plastic package layer. According to the invention, the interconnection among a plurality of chips is realized through the flexible conductive wire rod, the length of the interconnection wire can be obviously shortened, the influence on signal transmission is reduced, and the performance of the chip is improved.

Description

technical field [0001] The invention belongs to the technical field of chip packaging, and in particular relates to a multi-chip three-dimensional packaging structure and packaging method. Background technique [0002] At present, most integrated circuits adopt the form of planar packaging, that is, the packaging technology of integrating a single chip in the same plane. Due to the limitation of area, it is difficult to integrate multiple chips on the same plane. The so-called three-dimensional packaging is an emerging integrated circuit packaging technology in recent years, which breaks through the traditional concept of planar packaging. It is a package in which multiple chips are stacked in a single package in a three-dimensional space to package chips or bare chips. technology. However, the existing three-dimensional packaging technology basically adopts a "stacking + vertical conduction" packaging method for multiple chips. This packaging structure has the disadvantag...

Claims

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Application Information

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IPC IPC(8): H01L21/48H01L23/367H01L23/495H01L25/16
CPCH01L21/50H01L21/56H01L24/85H01L25/00H01L23/49811H01L23/367H01L23/3107H01L2224/85801
Inventor 赵迎宾杨斌崔成强
Owner 广东佛智芯微电子技术研究有限公司
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