Double-bit-line sub-threshold storage unit circuit

Abstract

The invention discloses a double-bit-line sub-threshold storage unit circuit which employs double-end read-write operation. The double-bit-line sub-threshold storage unit circuit comprises a first phase inverter and a second phase inverter, wherein the two phase inverters are connected to form a cross coupling; and by employing a double-bit-line structure of separating read bit lines from write bit lines, two storage nodes of the cross coupling are respectively connected to two write bit lines through an N-channel metal oxide semiconductor (NMOS) tube, and another two storage nodes of the cross coupling are respectively connected to two read bit lines through the NMOS tube and a P-channel metal oxide semiconductor (PMOS) tube. The double-bit-line sub-threshold storage unit circuit has the advantages that: by employing a PMOS substrate regulation technology, substrate ends of all PMOS tubes are connected to gate ends, so on the premise that additional management power consumption is not improved and the performance is not reduced, the energy consumption of dynamic operation and the leakage power consumption of static operation of a system can be reduced simultaneously, the static noise margin of a storage unit is improved, and the performance of the system is optimized.

Description

technical field [0001] The invention relates to a low-power storage unit under a sub-threshold working area in sub-threshold design, in particular to a double-bit line sub-threshold storage unit circuit, which belongs to the technical field of integrated circuit design. Background technique [0002] Static random access memory (SRAM) is an important part of modern digital systems, often occupying most of the system chip area, and often the power consumption bottleneck of system design. With the continuous improvement of the market's demand for various portable devices, higher requirements are put forward for the power consumption reduction technology of the memory cell array. Sub-threshold design is currently a hot topic in ultra-low power design. By reducing the power supply voltage VDD to enter the sub-threshold region of the circuit: the power supply voltage VDD is less than the threshold voltage Vth, making the system work in the linear region of the circuit, thereby si...

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Problems solved by technology

[0004] The problem to be solved by the present invention is: since the sub-threshold storage unit adopts a lower power supply voltage to obtain ultra-low energy consumption, it is more seriously affected by the process size and process deviation, and it is necessary to solve the problem that the noise tolerance of the storage unit is small , on the basis of ensuring a certain operating current to reduce the leakage current of the memory cell

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