Double-bit-line sub-threshold storage unit circuit

A memory cell circuit and sub-threshold technology, applied in the field of dual-bit line sub-threshold memory cell circuits and low-power memory cells, can solve the problems of small noise tolerance of memory cells, reduce leakage current of memory cells, etc., and improve charging and discharging. speed, the effect of reducing static leakage current, and reducing leakage power consumption

Inactive Publication Date: 2012-07-04
ANHUI UNIVERSITY
View PDF3 Cites 14 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The problem to be solved by the present invention is: since the sub-threshold storage unit adopts a lower power supply voltage to obtain ultra-low energy consumption, it is more seriously affected by the process size

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Double-bit-line sub-threshold storage unit circuit
  • Double-bit-line sub-threshold storage unit circuit
  • Double-bit-line sub-threshold storage unit circuit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0026] see figure 1 , the memory unit circuit of the present invention is made up of ten transistors (10T): four PMOS transistors P1, P2, P3, P4 and six NMOS transistors N1~N6, constitute the subthreshold value memory unit circuit of double-terminal read and write, have double-bit Line structure, that is, a pair of write bit lines and a pair of read bit lines.

[0027] Among them, the body terminals (substrates) of the four PMOS transistors are respectively connected to their gate terminals, and the body terminals of the six NMOS transistors are grounded to GND; the drain terminal and the gate terminal of the NMOS transistor N1 are respectively connected to the drain terminal and the gate terminal of the PMOS transistor P1 together to form the first inverter; the drain terminal and the gate terminal of the NMOS transistor N2 are respectively connected with the drain terminal and the gate terminal of the PMOS transistor P2 to form the second inverter; the first inverter and the...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a double-bit-line sub-threshold storage unit circuit which employs double-end read-write operation. The double-bit-line sub-threshold storage unit circuit comprises a first phase inverter and a second phase inverter, wherein the two phase inverters are connected to form a cross coupling; and by employing a double-bit-line structure of separating read bit lines from write bit lines, two storage nodes of the cross coupling are respectively connected to two write bit lines through an N-channel metal oxide semiconductor (NMOS) tube, and another two storage nodes of the cross coupling are respectively connected to two read bit lines through the NMOS tube and a P-channel metal oxide semiconductor (PMOS) tube. The double-bit-line sub-threshold storage unit circuit has the advantages that: by employing a PMOS substrate regulation technology, substrate ends of all PMOS tubes are connected to gate ends, so on the premise that additional management power consumption is not improved and the performance is not reduced, the energy consumption of dynamic operation and the leakage power consumption of static operation of a system can be reduced simultaneously, the static noise margin of a storage unit is improved, and the performance of the system is optimized.

Description

technical field [0001] The invention relates to a low-power storage unit under a sub-threshold working area in sub-threshold design, in particular to a double-bit line sub-threshold storage unit circuit, which belongs to the technical field of integrated circuit design. Background technique [0002] Static random access memory (SRAM) is an important part of modern digital systems, often occupying most of the system chip area, and often the power consumption bottleneck of system design. With the continuous improvement of the market's demand for various portable devices, higher requirements are put forward for the power consumption reduction technology of the memory cell array. Sub-threshold design is currently a hot topic in ultra-low power design. By reducing the power supply voltage VDD to enter the sub-threshold region of the circuit: the power supply voltage VDD is less than the threshold voltage Vth, making the system work in the linear region of the circuit, thereby si...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G11C11/40
Inventor 柏娜谭守标吴秀龙李正平孟坚陈军宁徐超代月花吴维奇
Owner ANHUI UNIVERSITY
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap