Memory system and method having selective ECC during low power refresh

Abstract

A computer system includes a processor coupled to a DRAM through a memory controller. The processor switches the DRAM to a low power refresh mode in which DRAM cells are refreshed at a sufficiently low rate that data retention errors may occur. Prior to switching the DRAM to the low power refresh mode, the processor identifies a region of an array of DRAM cells that contains essential data that needs to be protected from such data retention errors. The processor then reads data from the identified region, and either the DRAM or the memory controller generates error checking and correcting syndromes from the read data. The syndromes are stored in the DRAM, and the low power refresh mode is then entered. Upon exiting the low power refresh mode, the processor again reads the data from the identified region, and the read data is checked and corrected using the syndromes.

Description

TECHNICAL FIELD [0001] This invention relates to dynamic random access memory (“DRAM”) devices and systems, and, more particularly, to a method and system for allowing DRAM cells to be refreshed at a relatively low rate to reduce power consumption. BACKGROUND OF THE INVENTION [0002] As the use of electronic devices, such as personal computers, continue to increase, it is becoming ever more important to make such devices portable. The usefulness of portable electronic devices, such as notebook computers, is limited by the limited length of time batteries are capable of powering the device before needing to be recharged. This problem has been addressed by attempts to increase battery life and attempts to reduce the rate at which such electronic devices consume power. [0003] Various techniques have been used to reduce power consumption in electronic devices, the nature of which often depends upon the type of power consuming electronic circuits that are in the device. Electronic devices...

AI Technical Summary

Benefits of technology

[0009] A method and system for refreshing memory cells in a dynamic random access memory (“DRAM”) device is coupled to a processor in a computer system. The memory cells in the DRAM are refreshed at a reduced power rate that is sufficiently slow that data retention errors can be expected to occur during refresh. However, the expected data retention errors are corrected using ECC techniques applied only to memory cells containing essential data that should be protected from data retention errors. More specifically, prior to refreshing the memory cells at the reduced power rate, a determination is made, preferably by the...

Problems solved by technology

The memory cells in the DRAM are refreshed at a reduced power rate that is sufficiently slow that data retention errors can be expected to occur during refresh.

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