82results about How to "The formation process is simple" patented technology

A light-emitting device includes a first pixel, a second pixel, and a third pixel. The first pixel includes a first light-emitting element that emits light in a first wavelength range. The second pixel includes a second light-emitting element that emits light in a fourth wavelength range that is different from the first wavelength range and that includes a second wavelength range and a third wavelength range and a first color filter that transmits light in the second wavelength range emitted from the second light-emitting element. The third pixel includes a third light-emitting element that emits light in the fourth wavelength range and a second color filter that transmits light in the third wavelength range emitted from the third light-emitting element.

Embodiments of the invention generally relate to methods of forming flexible substrates for use in photovoltaic modules. The methods include shaping a metal foil and adhering the metal foil to a flexible backsheet. An optional interlayer dielectric and anti-tarnish material may then be applied to the upper surface of the shaped metal foil disposed on the flexible backsheet. The metal foil may be shaped using die cutting, roller cutting, or laser cutting techniques. The die cutting, roller cutting, and laser cutting techniques simplify the flexible substrate formation processes by eliminating resist-printing and etching steps previously used to pattern metal foils. Additionally, the die cutting, roller cutting, and laser cutting techniques reduce the consumption of consumable materials previously used in the patterning of metal foils.

A method for forming a write pole comprises forming a stop layer over a substrate layer of a wafer, the stop layer having an opening above a damascene trench in the substrate layer, and forming a buffer layer over the stop layer, the buffer layer having an opening above the opening of the stop layer. The method further comprises plating a layer of magnetic material over the wafer, disposing a first sacrificial material over a region of the magnetic material above the damascene trench, performing a milling or etching operation over the wafer to remove the magnetic material not covered by the first sacrificial material and to remove the first sacrificial material, disposing a second sacrificial material over the wafer, and performing a polishing operation over the wafer to remove the region of the magnetic material above the damascene trench, the second sacrificial material, and the buffer layer.

A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

A method of forming a dual self-aligned fully silicided gate in a CMOS device requiring only one lithography level, wherein the method comprises forming a first type semiconductor device having a first well region in a semiconductor substrate, first source/drain silicide areas in the first well region, and a first type gate isolated from the first source/drain silicide areas; forming a second type semiconductor device having a second well region in the semiconductor substrate, second source/drain silicide areas in the second well region, and a second type gate isolated from the second source/drain silicide areas; selectively forming a first metal layer over the second type semiconductor device; performing a first fully silicided (FUSI) gate formation on only the second type gate; depositing a second metal layer over the first and second type semiconductor devices; and performing a second FUSI gate formation on only the first type gate.

An electronic component includes at least one piezoelectric vibrating portion, a connecting portion provided on a substrate, a structural piece including a concavity so as not to disturb the vibration of the piezoelectric vibrating portion, and a connecting wiring for electrically connecting a pad on the substrate to a mounting wiring disposed on the upper surface of the structural piece. The structural piece further includes a through hole having an electroconductive material filled therein. The structural piece seals the piezoelectric vibrating portion.

The invention provides a synthetic method for symmetrical diaryl disulfide, which relates to the fields of organic chemical industry and fine chemical engineering. The method uses arylboronic acid and elemental sulfur powder as raw materials and a metallic copper salt as a catalyst; a reaction is carried out under the conditions of heating and stirring, and reaction time is 5 to 8 h; a mol ratio of arylboronic acid to elemental sulfur is 1: 1.5, the usage amount of the Cu catalyst is 5% of the mol fraction of the arylboronic acid, and an excellent effect is obtained when the raw materials react with the catalyst at a temperature of 50 to 80 DEG C for 5 to 8 h under stirring and heating. According to the invention, the inorganic substance, elemental sulfur, is used as a sulfur source, elemental sulfur and safe low-toxicity arylboronic acid undergo a coupling reaction to directly introduce an inorganic non-metallic element into an organic molecule, so greenness of synthetic route is realized; the reaction is easy to operate, the usage amount of the catalyst is small, the synthetic method is superior to other synthetic methods in the prior art, synthesized symmetrical diaryl disulfide is easy to separate, and good environmental protection performance is obtained.

The invention discloses a wafer level packaging method of a light emitting diode with an adjustable lens focus. The method comprises the following steps: in a first step, etching a light emitting diode lens mould microchannel array and a spacing control mould microchannel array surrounding a light emitting diode lens mould groove on a silicon wafer, and disposing proper amount of thermal outgassing agents in a light emitting diode lens mould microchannel; in a second step, carrying out anode bonding of the silicon wafer and a borosilicate glass water in vacuum to form a sealed cavity; in a third step, carrying out heating and heat preservation on a bonding wafer in the air, forming a spherical glass micro-cavity and a spacing control projection ring, carrying out cooling and annealing, and removing silicon to obtain a light emitting diode packaging lens array; in a fourth step, pasting a light emitting diode chip on a substrate; in a fifth step, bonding a wafer level glass micro-cavity and the substrate; in a sixth step, filling up glue into a gap between a light emitting diode chip and the wafer level glass micro-cavity through a spacing control ring gap, and carrying out solidification. The method can be carried out on a wafer level, and the method has the advantages of simplicity and low cost.

A non-volatile memory device includes a pair of source/drain regions disposed in a semiconductor substrate, having a channel region between them. A charge storage oxide layer is disposed on the channel region and overlaps part of each of the pair of source/drain regions. A gate electrode is disposed on the charge storage oxide layer. At least one halo implantation region is formed in the semiconductor substrate adjacent to one of the pair of source/drain regions, and overlapping the charge storage oxide layer. A program operation is performed by trapping electrons in the charge storage oxide layer located near the source/drain region where the halo ion implantation region is formed, and an erase operation is performed by injecting holes into the charge storage oxide layer located near the source/drain region where the halo ion implantation region is formed.

A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

A heated electrostatic chuck is provided, including a base having an upper surface and peripheral side surfaces, a thermal barrier coating formed by plasma deposition directly on at least the upper surface of the base, at least one heating element formed on portions of the thermal barrier coating, an electrically insulating layer formed on the heating element and exposed portions of the thermal barrier coating, at least one chucking electrode formed on at least a portion of the electrically insulating layer, and a protective layer formed on the chucking electrode.

The invention discloses an industrial control system as well as a control method and a control device thereof. The control method of the industrial control system comprises a data frame framing process and a data frame resolving process. The data frame framing process comprises the following steps of acquiring CAN (Controller Area Network) ID (Identity), data bits and data length according to variable names of external equipment; and framing data frames according to external equipment variable values as well as the CAN ID, the data bits and the data length. The data frame resolving process comprises the following steps of acquiring the data bits and the data length according to the CAN ID of data frames; and acquiring the external equipment variable values of the data frames according to the acquired data bits and data length. By utilizing the control method, by virtue of updating or increasing the information of an external equipment variable information group and a CAN data information group, the communication between the control device and the external equipment can be ensured, the data frame framing and the data frame resolving can be realized, while the universality of the control device is improved or kept, the assembling process of the industrial control system is simplified, and the stability and reliability of the industrial control system are improved.

The invention in one relates to a method for manufacturing a switchable particle-based display having a plurality of display units spatially arranged in a matrix form, wherein each display unit comprises one or more cells. In one embodiment, the method includes filling a plurality of first-type particles into the one or more cells of each display unit, filling one or more solutions into the one or more cells of each display unit, respectively, so that each cell contains one of the one or more solutions, where each of the one or more solutions comprises a respective colorant, and the respective colorant in each cell reacts with or adsorbs on the first-type particles therein, and filling a plurality of second-type particles into the one or more cells of each display unit.

A semiconductor device manufacturing method is provided in which, in the dummy gate pattern formation process, the pattern formation process is simplified and costs are reduced. A semiconductor device manufacturing method including: forming a mask element on a substrate; patterning the mask element into a prescribed shape, and forming a depression in the mask element; placing a functional liquid in the depression; drying the functional liquid placed in the depression so as to form a functional film; annealing the functional film; and, removing the mask element so as to form a dummy gate pattern of a residue of the functional liquid.

The invention, which belongs to the technical field of computers, provides a data processing method for a social network. The method comprises: user information, uploaded by an intelligent hardware device, of a specific user is obtained; the user information of the specific user is bound with the location information of the intelligent hardware device; a smart contract is issued; a blockchain bifurcation is established; statistics of specific users added into the blockchain bifurcation is carried out; a sub-virtual social network is formed; behavior data of members in the sub-virtual social network are recorded; structural processing is carried out on the behavior data to form various user portraits. With the method provided by the invention, the user's behavior data can be analyzed comprehensively; the user portrait formation process is simplified; and the novel social credit system is constructed based on the user portrait.

The embodiment of the invention provides a remote conference implementation method and system, and equipment. The method comprises: a shooting device is used for acquiring an identification code image, wherein the identification code image includes an identification code corresponding to the number of a second conference terminal and the second conference terminal is a terminal making a request ofparticipating in a remote conference in which a first conference terminal is currently located; according to the identification code in the identification code image, the number of the second conference terminal is obtained; the number of the second conference terminal is sent to a conference server, so that the conference server adds the second conference terminal in the conference in which thefirst conference terminal is currently located according to the number of the second conference terminal; or the identification code image is sent to the conference server and thus the conference server obtains the number of the second conference terminal based on the identification code in the identification code image, and the second conference terminal is added in a conference in which the first conference terminal is currently located based on the number of the second conference terminal. The remote conference implementation method and system, and equipment are used for improving the efficiency of organizing remote conferences.

A multiplexer/demultiplexer for at least two wavelengths in O-band. The multiplexer/demultiplexer includes a silicon waveguide block having a first port, a second/third port respectively in bar/cross position at an opposing end plane relative to the first port. The silicon waveguide block is configured to provide a general interference excitation of a light wave of a first wavelength and a second wavelength respectively selected from two windows in O-band. The light wave is either inputted via the first port and split into a first output light of the first wavelength out of the second port and a second output light of the second wavelength out of the third port, or is combined of a first input light of the first wavelength from the second port and a second input light of the second wavelength from the third port and outputted via the first port with both wavelengths.

A method for manufacturing a switchable PBD includes filling a plurality of first-type particles and a plurality of second-type particles into each cell, where the plurality of first-type particles carries charges of a first charge polarity having a first charge density and the plurality of second-type particles is substantially electrically neutral, or carries charges having a second charge density that is substantially lower than the first charge density of the first-type particles, and filling a fluid into each cell, where the fluid comprises a charge controlling agent having a second charge polarity opposite to the first charge polarity, and the charge controlling agent has a substantially selective wettability, absorbability or adsorbability on the plurality of second-type particles. As such, at least part of the plurality of second-type particles is charged to have the second charge polarity in each cell.

A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.