Method for forming self-aligned dual salicide in CMOS technologies

Abstract

A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

Description

CROSS REFERENCE TO RELATED APPLICATION [0001] This application relates to co-pending U.S. patent application Ser. No. ______ entitled “Method for Forming Self-Aligned Dual Fully Silicide Gates in CMOS Devices” (Docket No. FIS920040183US1), filed concurrently herewith, the contents of which in its entirety is herein incorporated by reference.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The embodiments of the invention generally relate to complementary metal oxide semiconductor (CMOS) device fabrication, and more particularly to a method of forming dual self-aligned silicide in CMOS technologies to improve device performance. [0004] 2. Description of the Related Art [0005] The term salicide, which stands for Self-ALIgned siliCIDE, refers to a silicide formed by a self-aligning method. A salicide is typically formed by depositing a metal layer (such as Ti, Co, Ni, etc.) over a silicon layer, and then annealing the semiconductor structure. Where the metal is in co...

AI Technical Summary

Benefits of technology

[0017] Generally, the embodiments of the invention provide a double self-aligning technique of forming a dual salicide (i.e., different salicide formations), such as NiSi, CoSi2, TiSi2, WSi2, PdSi, PtSi, TaSi2, ReSi, etc., and their alloys at the source / drain and gate areas for NFET and PFET regions of a CMOS device with only one lithography level. As such, the embodiments of the invention reduce the required lithography level, greatly simplify the dual salicide formation process, and eliminate the misalignment problem associated with some conventional techniques. Moreover, the embodiments of the invention enable the optimization of the performance of the CMOS device by forming one salicide in the NFET region and a different salicide in the PFET region.

Problems solved by technology

However, one of the drawbacks of this approach is non-optimal device performance when compared with a dual salicide approach.

However, one of the problems with the conventional two lithography level dual salicide process as provided in FIGS. 2-4 is the misalignment caused during the processing between the two lithography levels as illustrated in FIG. 5 (the dotted circle represents the area of the device 1 where the misalignment occurs).

This misalignment between the NFET region 40 and PFET region 30 results in an underlay in the device 1 (illustrated in FIG. 5 as a SRAM (synchronous random access memory) cell layout), which can cause high sheet resistance or an open circuit in the device and / or circuit areas thereby resulting in inferior device / circuit performance.

Images