Printed circuit board layout method, product, equipment and readable storage medium

Abstract

The invention discloses a layout method of a printed circuit board, a product, equipment and a readable storage medium, and relates to the technical field of PCB design, and the method comprises the steps: carrying out the optimization decoupling and optimization separation of a position layout and a rotation angle into independent stages of sequential execution, avoiding the mutual interference of two types of decisions, greatly reducing the search space, and improving the convergence efficiency. After newly-added elements are placed every time, all the placed elements on the current board are subjected to rotation optimization, the accumulated influence of default direction deviation of early-stage elements on subsequent layout is eliminated, the optimal solution is gradually approached through multi-round iteration, the total length of a finally-arranged wire net is reduced, the signal transmission performance of the PCB is remarkably improved, and the reliability of the PCB is improved. Therefore, the problem of irreversible influence of early decision on subsequent layout is solved, and the beneficial effects of improving layout quality and optimizing PCB circuit performance are achieved.

Description

Technical Field

[0001] The present application relates to the field of PCB design technology, and in particular to a printed circuit board layout method, product, device, and readable storage medium. Background Art

[0002] PCBs (Printed Circuit Boards) are used to carry various electronic components to implement circuit functions. The main stages of PCB design include schematic design and layout design. Layout design is further divided into two key steps: layout and routing. The quality of layout not only directly affects the complexity and quality of routing, but also affects the PCB's area utilization, power consumption, and heat dissipation performance. In current layout schemes, once a component's orientation is determined during placement, it cannot be modified in subsequent stages. Suboptimal component orientation selection will affect the overall layout quality.

[0003] Therefore, how to provide a solution to the above technical problems is a problem that those skilled in the art need to solve at present. Summary of the Invention

[0004] The present application provides a printed circuit board layout method, product, device and readable storage medium to at least solve the problem in related technologies that early decisions have irreversible effects on subsequent layouts.

[0005] The present application provides a layout method for a printed circuit board, comprising: based on a layout state of the printed circuit board in a current iteration, selecting a component to be placed from a set of unplaced components in the current iteration, and determining a placement position of the component to be placed on the printed circuit board; placing the component to be placed at the placement position in a default direction, and updating the layout state; for each component to be optimized in the updated layout state, determining an optimal rotation angle of the component to be optimized, rotating the component to be optimized from the current placement direction by the optimal rotation angle to obtain a preferred placement direction, updating the layout state, and entering the next iteration; outputting the placement position and placement direction of each component in the last iteration as a final layout plan for the printed circuit board, wherein the set of unplaced components in the last iteration is empty.

[0006] The present application also provides a computer program product, comprising a computer program, which implements the steps of any of the above-mentioned printed circuit board layout methods when executed by a processor.

[0007] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned printed circuit board layout methods when executing the computer program.

[0008] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned printed circuit board layout methods are implemented.

[0009] This application decouples position layout from rotation angle optimization, separating the optimization into independent, sequentially executed stages. This avoids interference between the two types of decisions, significantly reduces the search space, and improves convergence efficiency. Each time a new component is placed, rotation optimization is performed on all previously placed components on the current board, eliminating the cumulative impact of early component default orientation deviations on subsequent layouts. Through multiple rounds of iteration, the optimal solution is gradually approached, and the total length of the final layout wire network is reduced, significantly improving the signal transmission performance of the PCB circuit. This solves the problem of irreversible effects of early decisions on subsequent layouts, achieving the beneficial effect of improving layout quality to optimize PCB circuit performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0011] Figure 1 A flowchart of the steps of a printed circuit board layout method provided in an embodiment of the present application.

[0012] Figure 2 A schematic diagram of placement direction provided in an embodiment of the present application.

[0013] Figure 3 A schematic diagram of node expansion provided in an embodiment of the present application.

[0014] Figure 4 A schematic diagram of pin feature construction provided in an embodiment of the present application.

[0015] Figure 5 A schematic structural diagram of a printed circuit board layout device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0016] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0017] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0018] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0019] The embodiment of the present application provides a layout method for a printed circuit board, Figure 1 , a layout method of the printed circuit board is described in detail.

[0020] S101: Based on the layout state of the printed circuit board in the current iteration, select a component to be placed from the set of unplaced components in the current iteration, and determine the placement position of the component to be placed on the printed circuit board.

[0021] First, the relevant information of the printed circuit board is described. The relevant information of the printed circuit board includes at least the size information of the printed circuit board. The printed circuit board can be discretized into grid points. In this embodiment, It is defined as the set of locations after the printed circuit board is discretized. For example, the printed circuit board is discretized as , then , the placement direction of the components on the printed circuit board is O, each component can be adjusted in the following four directions but not limited to , respectively represent the default orientation of the component and the orientation after clockwise rotation of different angles, where 0 means using the default orientation in the packaging process library, 90 means rotating the default orientation 90 degrees clockwise, and so on. ) to indicate the placement position of the component on the printed circuit board, and rot to indicate the placement direction of the component on the printed circuit board (including but not limited to using the default direction in the package process library, rotating the default direction 90 degrees clockwise, rotating the default direction 180 degrees clockwise, or rotating the default direction 270 degrees clockwise, such as Figure 2 shown).

[0022] As will be appreciated, to improve the reliability of component layout on the printed circuit board, this embodiment uses an iterative approach to update the placement and orientation of each component on the printed circuit board. Prior to the iteration, information related to the printed circuit board, a component list, and a netlist are first obtained. The component list includes size information (height and width) and pin information. The netlist consists of several nets, each of which includes a driver pin and one or more load pins.

[0023] First determine the layout status of the printed circuit board in the current iteration and unplaced component collections , Indicates the number of iterations. If the current iteration is the first iteration, then , the layout status of the printed circuit board is ,initialization , N is the total number of elements in the element list. If the current iteration is the fifth iteration, then , the layout status of the printed circuit board is , the set of unplaced components is Among them, the layout state of the printed circuit board includes the collective state of the placement positions and placement directions of all placed components on the printed circuit board in the current iteration. Its initial state ( ) is an empty board. The unplaced component set refers to the set of components that have not yet been placed on the printed circuit board in the current iteration. Its initial state is the complete set of all components to be placed.

[0024] Based on the layout status of the printed circuit board in the current iteration , from the non-empty Select a component c to be placed and determine the placement position of the component c on the printed circuit board. The placement position is determined by the discretized grid coordinates ( ), where x and y are integers representing the specific location of the component c to be placed in the grid system of the printed circuit board. When selecting a component c to be placed, the selection may be made according to a preset optimization strategy or randomly selected, which is not specifically limited in this embodiment.

[0025] For example, suppose this is the first iteration ( ), layout status It is an empty board, and no component set is laid out. It contains three components, namely The goal of this step is to Select a component as the component to be placed c, such as resistor R, and determine its placement position. The output of this step is that the component to be placed is resistor R, and its placement position is .

[0026] S102: Place the component to be placed at the placement position according to the default direction and update the layout status.

[0027] It is understood that the default direction refers to the initial orientation of the component to be placed defined in the package process library, usually recorded as a rotation angle , represents the standard placement posture of the component without any rotation transformation. After placing the component c to be placed in its corresponding placement position according to the default direction, it is equivalent to updating the component layout on the printed circuit board. A component placed in the default direction is added to the printed circuit board. At this time, the layout status is updated. Update, the status of the layout after this update is The process of updating the layout state includes but is not limited to the following: ) and placement direction ) added to the layout state middle.

[0028] For example, assuming the component c to be placed is a resistor R, its placement position is ( ). This step first rotates the resistor R to its default orientation (rotation angle )Place on the printed circuit board ( ) coordinate grid. Then, execute the layout status update operation to update the component identifier (R), position ( ) and direction ( ) as a new record entry, added to the layout state In, get . Also, the component collection is never placed ( ) to remove the component R. For example, if the update , If it is an empty board, then after updating , It can be understood that the updated , as the next iteration, i.e. The set of unplaced components in iteration .

[0029] In this example, the selected components are initially placed in a default orientation, providing a stable and reasonable starting point for subsequent refined orientation optimization and avoiding optimization difficulties caused by improper initial orientation. Furthermore, real-time updates to the layout state ensure that each decision is based on the latest global information, maintaining data integrity during the iterative process and laying the foundation for an efficient and automated layout process.

[0030] S103: For each component to be optimized in the updated layout state, determine the optimal rotation angle of the component to be optimized, rotate the component to be optimized from the current placement direction by the optimal rotation angle to obtain the preferred placement direction, and update the layout state to enter the next iteration.

[0031] In this embodiment, considering that a component c to be placed is added to the updated layout state, that is, a new component c to be placed is placed on the printed circuit board, the component layout on the printed circuit board has changed. At this time, the components already placed on the printed circuit board may need to be readjusted in their placement direction to achieve the optimal layout strategy. Therefore, in this embodiment, the updated layout state Each component included in is defined as a component to be optimized. The optimal rotation angle corresponding to each component to be optimized is determined in turn. The component to be optimized is rotated from the current placement direction to the optimal rotation angle to obtain the preferred placement direction of the component to be optimized in the current iteration. After all components to be optimized are placed according to their preferred placement directions, the layout update of the printed circuit board in the current iteration is completed. At this time, the updated layout status is obtained. , as the next iteration, i.e. The state of the layout in iteration .

[0032] Still taking the first iteration as an example, since only one component c is placed, after placing the component c in the default direction, the layout status is updated to At this time, since there is only one component to be optimized on the printed circuit board (that is, component c to be placed), after adjusting the placement direction of the component to be optimized, the layout state is updated and the result is , Compared to , adjusted The direction of placement of components, such as Based on this step, the preferred placement direction of the resistor R is determined to be rotated from the default direction ,but It can be understood that for the component c to be placed, its current placement direction is the default direction, and for other placed components on the printed circuit board in the current iteration, their current placement direction is the preferred placement direction determined in the previous iteration.

[0033] In this embodiment, the placement orientation of components already placed on the printed circuit board is adjusted to the preferred placement orientation with each iteration to support the retrospective nature of orientation decisions, thereby avoiding adverse effects of early orientation decisions on the overall layout quality, and continuously approaching the overall optimal solution during the iteration process.

[0034] S104: Outputting the placement position and placement direction of each component in the last iteration as the final layout plan of the printed circuit board. The set of unplaced components in the last iteration is empty.

[0035] In this embodiment, when the iteration process meets the termination condition, that is, the set of unplaced components in the current iteration is an empty set, then the current iteration is the last iteration. At this time, all components have been placed on the printed circuit board, the iteration is terminated, and the final layout solution is output.

[0036] It can be understood that the final layout solution is defined by the layout state after the last iterative update, which fully records the coordinates of the final placement position of each component and its final preferred placement direction. This embodiment ensures that the output is a complete and optimized layout solution through iterative optimization and termination condition judgment. It not only meets the physical constraints of all component placement, but also achieves a high-quality solution under multiple objective trade-offs such as wiring length, signal integrity, heat dissipation performance, and neatness through multiple coordinated optimizations of direction and position. The machine readability and structured characteristics of the output results significantly improve the conversion efficiency from design to production, reduce manual intervention, and improve the efficiency of fully automatic layout of printed circuit boards.

[0037] In an exemplary embodiment, a process of selecting a component to be placed from a set of unplaced components in a current iteration based on a layout state of a printed circuit board in a current iteration includes: constructing a first root node using the layout state of the printed circuit board in the current iteration and the set of unplaced components as node attributes; creating at least one child node for the first root node based on at least one unplaced component in the set of unplaced components; executing a first search loop operation starting from the first root node to update the number of selections of each child node under the first root node; and when the number of executions of the first search loop operation reaches a preset number, sampling is performed in a probability distribution determined based on the number of selections of each child node under the first root node to obtain the component to be placed.

[0038] For ease of understanding, this embodiment illustrates the process of determining the components to be placed during one iteration, and the same applies to other iterations.

[0039] In this embodiment, the components to be placed can be obtained by decision by the first agent P. The decision-making process of the first agent P is as follows: first, the layout state of the printed circuit board in the current iteration and the set of unplaced components are used as node attributes to construct the first root node. The first root node is the node in the search tree that serves as the starting point of the search. It contains information such as the initial layout state and the set of unplaced components. This ensures that the component selection process can fully consider the overall progress and remaining possibilities of the layout process, avoiding the limitations of isolated decisions. Based on the number of components in the set of unplaced components, a corresponding number of child nodes are created for the first root node. Each child node corresponds to an unplaced component. For example, assuming that the current iteration is the first iteration ( ), layout status It is an empty board, and no component set is laid out. It contains three components, namely , then the attributes of the first root node r1 include and , creating three child nodes for the first root node: the first child node v1 corresponding to the resistor, the second child node v2 corresponding to the capacitor, and the third child node v3 corresponding to the inductor. By creating child nodes representing different component selection options for the first root node, the selection problem is transformed into a structured search space, making the decision process clear, manageable, and optimizable.

[0040] The first agent P starts from the first root node and executes a preset number of first search loop operations (such as Monte Carlo tree search). Each loop includes at least four stages: selection, expansion, simulation and backtracking. By executing the preset number of first search loop operations, the number of times each option (child node) is selected is updated, so that the final decision does not rely on a single calculation or random guessing, but is based on statistical evidence accumulated from multiple simulation evaluations, thereby improving the reliability and robustness of the decision.

[0041] When the search loop executes a preset number of times, a probability distribution is calculated based on the number of visits to each child node under the first root node, and sampling is performed to determine the final component to be placed. Sampling based on the probability distribution formed by the number of times each child node has been selected favors the solution with the best historical performance (the most frequent selections) while retaining a certain degree of randomness to explore other potential options. This achieves a good balance between leveraging known good solutions and exploring potentially better solutions.

[0042] For example, assume that the set of unplaced components in the current iteration is [capacitor C, inductor L], and the layout state is a layout with resistor R placed. After constructing the first root node, two child nodes are created for it: the first child node (selecting capacitor C) and the second child node (selecting inductor L). After 10 first search loop operations, it is shown that the first child node is accessed 6 times and the second child node B is accessed 4 times. The probability of selecting capacitor C is , the probability of selecting inductor L is 0.4, and the components to be placed are sampled in the corresponding probability interval.

[0043] The first search loop operation includes: selecting a first optimal node from all child nodes under the first root node according to the selected values of the child nodes under the first root node in the current first search loop operation, and updating the access times of the first root node and the selection times of the child nodes under the first root node; if the first optimal node is a leaf node, determining the placement position of the first optimal node on the printed circuit board through a first preset neural network strategy, placing the un-laid component corresponding to the first optimal node on the placement position corresponding to the first optimal node to obtain a first intermediate layout state; optimizing and adjusting the placement direction of the components in the first intermediate layout state by using a second preset heuristic strategy to obtain a second intermediate layout state; removing the un-laid component corresponding to the first optimal node from the un-laid component set to obtain a new un-laid component set; taking the second intermediate layout state and the new un-laid component set as node attributes, constructing a first intermediate node, and adding the first intermediate node to the child node of the first optimal node; if the new un-laid component set is not empty, creating at least one first intermediate child node for the first intermediate node based on at least one un-laid component in the new un-laid component set; determining the placement position and the placement direction of the un-laid component corresponding to the first intermediate child node on the printed circuit board through the first preset neural network strategy, the first preset heuristic strategy and the second preset heuristic strategy; determining a first intermediate layout based on the placement position and the placement direction of each un-laid component in the un-laid component set in the current iteration, calculating the evaluation value of the first intermediate layout; and updating the selected value of each child node under the first root node by using the evaluation value, so as to enter the next first search loop operation.

[0044] In this embodiment, the strategy of the first intelligent agent P can be formalized as wherein, represents a certain layout state in the current iteration, represents a component set that has not been placed in the current iteration, is a first preset neural network strategy for position decision, is a learnable parameter, is a heuristic strategy for determining the layout order (such as preferentially selecting a component with a large area), is a heuristic strategy for adjusting the direction of the placed component (for example: rotating the component that can improve the optimization target f the most each time until it cannot be further improved).

[0045] The first search loop operation in this embodiment refers to an iterative search process based on a tree structure, and the core steps include selection, expansion, simulation and backtracking. The first first search loop operation is described below, and the same applies to each subsequent first search loop operation.

[0046] Among them, before selecting the first optimal node from all the child nodes under the first root node according to the selected values ​​of each child node under the first root node in the current first search cycle operation, the layout method of the printed circuit board also includes: if the current first search cycle operation is the first first search cycle operation, the selected value of the child node under the first root node is 0; if the current first search cycle operation is not the first first search cycle operation, the selected value of the child node under the first root node is the selected value updated based on the evaluation value in the previous first search cycle operation; the process of selecting the first optimal node from all the child nodes under the first root node according to the selected value of each child node under the first root node in the current first search cycle operation includes: for each child node under the first root node, obtaining the decision value of the child node under the first root node based on the selected value and the search reward value of the child node under the first root node in the current first search cycle operation; the search reward value is determined based on the number of visits to the first root node and the number of selections of the child node under the first root node by the child node under the first root node that has not been updated in the current first search cycle operation; and determining the child node with the largest decision value as the first optimal node.

[0047] For example, it is assumed that the current iteration is the first one ( ), layout status It is an empty board, and no component set is laid out. It contains three components, namely , initialize the first root node r1, the first root node r1 contains the initial layout state (The layout is empty at this time) and a collection of unplaced components The first search loop operation starts, and the first optimal node is selected according to the selected value of each child node under the first root node r1. Assume that there are three child nodes under the first root node, each representing a different layout decision direction, which are the first child nodes corresponding to the selected resistor. , the second sub-node corresponding to the selected capacitor , the third child node corresponding to the selected inductor , by calculating 、 and The selected value, from 、 and A child node is selected as the first optimal node.

[0048] Specifically, the first optimal node can be selected based on the first relational expression, where the first relational expression is ; is the first optimal node, The child node set of the first root node (in the above example, including 、 and ), is the selected value of a child node vr1 under the first root node r1, is the search reward value of a child node vr1 under the first root node r1, where , To explore the reward coefficient, is the number of visits to the first root node r1, The number of times a child node vr1 is selected under the first root node r1, that is, the number of times the child node vr1 is selected.

[0049] Considering that in the first search loop operation, the number of times r1 is accessed is is 0, Number of times selected 、 Number of times selected and Number of times selected are all 0, so The decision value of 、 The decision value of and The decision value of Equal. Then the first optimal child node can be 、 and Randomly select one from the ,but The number of times selected is increased by 1, and the number of visits to r1 is also increased by 1. When the second first search loop operation is performed, the number of visits to r1 is updated to 1. The number of times selected is updated to 1, and The number of times selected is still 0, and the decision value of each child node is calculated based on the updated value to select the first optimal child node in the second search cycle operation process.

[0050] If the first optimal node For leaf nodes, i.e. nodes that do not include expansion nodes, the first preset neural network strategy is used Determine the first optimal node Corresponding unplaced components Placement on the printed circuit board, specifically, based on the prediction For example, the neural network model calculates that the component should be placed in the upper left corner of the layout based on the current layout status and component characteristics, and then Place it in this position The first intermediate layout state is obtained.

[0051] Then a second preset heuristic strategy is used to perform an optimal adjustment of the placement direction of the elements in the first intermediate layout state, for example, for the just-placed elements, the heuristic strategy is used to perform a rotation adjustment, the optimal target value is calculated after each rotation, the rotation direction that maximizes the optimal target value is selected, and the process is terminated when the optimal target value cannot be further improved, to obtain a second intermediate layout state.

[0052] The unplaced elements corresponding to the first optimal node are removed from the unplaced element set to obtain a new unplaced element set. The second intermediate layout state and the new unplaced element set are used as node attributes to construct a first intermediate node, and the first intermediate node is added to the child nodes of the first optimal node. If the new unplaced element set is not empty, a first intermediate child node is created for the first intermediate node based on the unplaced elements in the new unplaced element set. The placement position and the placement direction of each unplaced element in the new unplaced element set on the printed circuit board are determined by a first preset neural network strategy , a first preset heuristic strategy and a first preset heuristic strategy , wherein the next first intermediate child node is selected by the first preset heuristic strategy , the placement position of the selected first intermediate child node is determined by , and the placement direction of the selected first intermediate child node is adjusted by the second preset heuristic strategy .

[0053] A first intermediate layout is determined based on the placement position and the placement direction of each unplaced element in the unplaced element set of the current iteration, and an evaluation value of the first intermediate layout is calculated. The evaluation value is used to update the selected value of each child node under the first root node, so as to enter the next first search loop operation.

[0054] As shown in Figure 3 , assuming is the root node (r), the initial layout state in the current iteration can be , the unplaced element set under includes , and the child nodes under correspond to the selected elements , correspond to the selected elements , correspond to the selected elements .Corresponding selection components , The child node below Corresponding selection components , The first optimal node selected in the first search cycle operation, the decision corresponding to this node is to select and place the component ,Will Corresponding components Eliminate from the set of unplaced components to obtain a new set of unplaced components . Construct the first intermediate node with the second intermediate layout state and the new set of unplaced components as node attributes , and the first intermediate node Add to Among the child nodes of If it is a node that has not been expanded, then for the first intermediate node Perform the expansion operation to obtain the first intermediate node Child nodes of , Same reason.

[0055] Repeating the above steps multiple times, each execution of the first search loop will select the first optimal node, place and adjust components, and calculate and update evaluation values ​​based on information such as the current layout state and the set of unplaced components, gradually optimizing the layout of the entire printed circuit board until a preset termination condition is met, such as reaching a preset number of iterations or a satisfactory layout evaluation value. In this embodiment, a tree structure search, a neural network strategy, and a heuristic strategy are combined to achieve intelligent optimization of the printed circuit board layout, capable of automatically selecting the optimal component placement order, position, and direction, significantly improving layout efficiency and quality. The iterative optimization process can dynamically update node values ​​and evaluation results in each search loop, gradually approaching the global optimal solution, effectively reducing manual intervention, improving the level of automation, and being suitable for complex and changing actual engineering scenarios.

[0056] As an optional embodiment, if the first root node or the first intermediate node is not expanded, and the depth (distance from the first root node) does not exceed the threshold (preset hyperparameter), and the set of unplaced components corresponding to the first root node or the first intermediate node is not empty, then the expansion operation of the node is performed.

[0057] In an exemplary embodiment, the process of using the evaluation value to update the selected value of each child node under the first root node includes: determining the nodes to be updated on the search path of the current first search loop operation; for each node to be updated, based on the evaluation value, the number of visits to the node to be updated, and the selected value of the node to be updated when it is not updated in the current first search loop operation, obtaining the selected value of the node to be updated after being updated in the current first search loop operation.

[0058] In this embodiment, each node to be updated along the search path Update in sequence, t is the index of the edge in the path, and the search path is the node sequence starting from the root node and reaching the leaf node in a certain first search loop operation.

[0059] .

[0060] .

[0061] .

[0062] For example: , where the above example is still used as an example to illustrate, Represents the root node, This means that the resistor is selected as the first layout element. Indicates the state after the resistor is placed. Indicates that the capacitor is selected as the second layout element. Represents the state after placing the capacitor, that is, the leaf node, at this time the value of t is 0, 1. Backtracking from the leaf node, update each pair of nodes on the path, the first step is to update ( ), the second step updates ( ).in, Indicates the current number of search loop operations. That is the first search loop operation, That is the second search cycle operation, It indicates the last search cycle operation, k is the preset number of times, and so on.

[0063] In an exemplary embodiment, when the number of executions of the first search loop operation reaches a preset number, sampling is performed in a probability distribution determined based on the number of selections of each child node under the first root node to obtain the process of components to be placed, including: when the number of executions of the first search loop operation reaches a preset number, after transforming the number of selections of each child node under the first root node according to the temperature coefficient, sampling is performed in each child node under the first root node according to the obtained probability distribution to obtain components to be placed.

[0064] In this embodiment, after completing k searches, sampling is performed from the child nodes of the first root node r1 according to the following distribution: ;in, To control the temperature coefficient of exploration and utilization, is the number of times the currently selected child node vr1 under the first root node r1 is selected, For each child node under the first root node r1 The number of selections, the element corresponding to the sampled node v This is the component you select to be placed.

[0065] In this embodiment, by combining a neural network strategy with a heuristic strategy, the placement and orientation of components can be quickly determined. This significantly improves layout efficiency and shortens the design cycle of printed circuit boards compared to traditional purely manual layout or simple heuristic layout methods. The neural network strategy can learn from a large amount of layout data, thereby better understanding the relationships between components and the global characteristics of the layout, and generating more optimal layout solutions. Simultaneously, the heuristic strategy also plays an important role in local optimization, such as prioritizing the placement of large components and fine-tuning component orientation. This further improves the quality of the layout, making the final layout more compact and reasonable, reducing the connection length between components, improving signal transmission efficiency, and reducing electromagnetic interference.

[0066] In an exemplary embodiment, the process of determining the placement position of the component to be placed on the printed circuit board includes: using a first preset neural network strategy to determine the placement position of the component to be placed on the printed circuit board, wherein the first preset neural network strategy includes: representing the layout state of the printed circuit board in the current iteration as a binary image; the pixel value of the pixel position in the binary image represents the occupancy state of the pixel position; using an image encoder to extract high-level features of the binary image to obtain a global representation vector; for each pixel position in the binary image, calculating the change in the objective function when the component to be placed is placed at the pixel position; obtaining a target change graph based on all target function changes, dividing the target change graph into several blocks, each block including multiple pixel positions; encoding each block to obtain a feature vector of the block; calculating the probability distribution of the placement position of the component to be placed based on the correlation between the global representation vector and the feature vector of each block, and the target function change corresponding to each pixel position; and determining the placement position of the component to be placed according to the probability distribution.

[0067] In this embodiment, the first preset neural network strategy is used To predict the placement of components to be placed , the final return result is: component and its placement .

[0068] Next, the first preset neural network strategy Explain the decision-making plan. The goal is to predict the optimal placement position of component i in the layout of the printed circuit board given the current layout state s and the component i to be placed.

[0069] First, the current layout state s is represented as a binary image img, whose dimensions are consistent with the layout space. In this binary image img, a pixel value of 0 indicates that the corresponding position is not occupied, and a pixel value of 1 indicates that the corresponding position is occupied by another component. Then, an image encoder (such as a residual network ResNet) is used to extract high-level features from this binary image img to obtain the global representation vector of the current layout state s. .

[0070] The decision process is as follows: construct a feature map, and , consider placing the center point of element i at this position and calculate the change in the objective function: ;in, is the objective function value under the current layout state s, To place component i at pixel position The objective function value after , can be used to obtain a target change graph with the same layout size.

[0071] The target change map is divided into several fixed-size blocks (i.e., blocks in this embodiment), each block is denoted as p, and each block p contains multiple pixels. For each block p, flatten it into a vector .

[0072] Calculate the small block features and introduce a learnable feedforward neural network FNN to encode the representation of each small block to obtain its feature vector .

[0073] Calculate the location distribution: ; Where p is the pixel position The first half of the formula is the probability of selecting a small block p, and the second half is the probability of selecting a pixel position in the small block p. The probability of is a learnable linear mapping matrix, Represents each of the small blocks, is each pixel position in the small block p.

[0074] This embodiment encodes the layout state into a binary image and uses a deep encoder to extract global features, so that the system can understand the overall structural characteristics and constraint relationships of the layout space, provide contextual information for position decisions, and convert the abstract optimization target into a concrete target change map by calculating the change in the objective function of each pixel position and generating a target change map, thereby achieving a direct mapping between the optimization target and the spatial position. Finally, by dividing the target change map into blocks and encoding them separately, and then calculating the correlation with the global features, the fine gradient information of the local area is retained and the semantic information of the global layout is integrated. The resulting probability distribution not only reflects the immediate benefit of the local position, but also reflects the long-term value of the position in the global layout, thereby greatly improving the search efficiency while ensuring the layout quality, and effectively balancing the solution accuracy and computational efficiency.

[0075] In an exemplary embodiment, for each element to be optimized in the updated layout state, the process of determining the optimal rotation angle of the element to be optimized includes: determining a set of unoptimized elements in the updated layout state; when the unoptimized element set is empty, outputting a rotation trajectory, the rotation trajectory including the element to be optimized selected for each rotation and the optimal rotation angle corresponding to the element to be optimized; when the unoptimized element set is not empty, selecting an unoptimized element from the unoptimized element set as the element to be optimized for the current rotation operation, determining the optimal rotation angle of the element to be optimized, removing the element to be optimized for the current rotation operation from the unoptimized element set, updating the layout state, and repeating the operation of determining the set of unoptimized elements in the updated layout state.

[0076] In this embodiment, components to be optimized refer to components whose optimal rotation angles for the current iteration have not yet been determined in the updated layout state after the selected components are placed on the printed circuit board in the default orientation. The rotation angles of these components need to be determined through the optimization process to achieve a better layout effect. The unoptimized component set is a set containing all components to be optimized. During the optimization process, one component is selected from this set each time for rotation angle optimization until the unoptimized component set is empty. An empty unoptimized component set indicates that the rotation angles of all components in the current iteration have been optimized.

[0077] It can be understood that the optimal rotation angle is the most suitable rotation angle calculated for each component to be optimized through a certain optimization strategy. This angle can make the layout state reach the best or better state in certain optimization goals (such as layout compactness, signal integrity, etc.).

[0078] The optimal rotation angle in this embodiment can be obtained based on the decision of the second agent R. The strategy of the second agent R is formalized as ,in, A certain layout state in the current iteration. The set of components that have not yet been rotated in the current iteration, is the neural network strategy for direction decision making, are learnable parameters.

[0079] The policy output of the second agent R is ;in, exist The number of components placed on Indicates the element selected by the 0th rotation operation, express The optimal rotation angle in the current iteration, and so on.

[0080] The main decision-making process is as follows: S1: If If it is empty, go to S3. Not empty, go to S2, ; S2: Call sub-decision process: from Select component j and determine its optimal rotation angle , remove element j from the queue Remove from, get , and update the layout status, return to S1; S3: return to the rotation trajectory .

[0081] In an exemplary embodiment, the process of selecting a non-optimized element from a non-optimized element set as the element to be optimized for the current rotation operation includes: constructing a second root node with the layout state and the non-optimized element set corresponding to the current rotation operation as node attributes; creating at least one child node for the second root node based on at least one non-optimized element in the non-optimized element set; and executing a second search loop operation starting from the second root node to update the number of selections of each child node under the second root node; when the number of executions of the second search loop operation reaches a preset number, sampling is performed in a probability distribution determined based on the number of selections of each child node under the second root node to obtain the element to be optimized for the current rotation operation.

[0082] It can be understood that the difference between the process of selecting the next component to be optimized from the set of unoptimized components and the process of selecting the next component to be placed from the set of unplaced components lies in the second search loop operation and the preset neural network strategy used to select the component to be optimized. As for the selection process, the two are basically the same. Please refer to the process of selecting the next component to be placed from the set of unplaced components above, and no further details will be given here.

[0083] Among them, the second search loop operation includes: selecting the second optimal node from all the child nodes under the second root node according to the selected values ​​of each child node under the second root node in the current second search loop operation, and updating the number of visits to the second root node and the number of selections of each child node under the second root node; if the second optimal node is a leaf node, determining the optimal rotation angle of the second optimal node on the printed circuit board through the second preset neural network strategy, adjusting the placement direction of the non-optimized component corresponding to the second optimal node at its placement position according to the optimal rotation angle of the second optimal node on the printed circuit board, and obtaining a third intermediate layout state; eliminating the non-optimized component corresponding to the second optimal node from the non-optimized component set to obtain a new non-optimized component set; using the third The intermediate layout state and the new unoptimized component set are used as node attributes to construct a second intermediate node, and the second intermediate node is added to the child node of the second optimal node; if the new unoptimized component set is not empty, at least one second intermediate child node is created for the second intermediate node based on at least one unoptimized component in the new unoptimized component set; the placement direction of the unoptimized component corresponding to the second intermediate child node on the printed circuit board is determined by a second preset neural network strategy; the second intermediate layout is determined based on the placement direction of each unoptimized component in the unoptimized component set corresponding to the current rotation operation, and a second evaluation value of the second intermediate layout is calculated; the second evaluation value is used to update the selected value of each child node under the second root node so as to enter the next second search loop operation.

[0084] In this embodiment, the difference between the second search cycle operation and the first search cycle operation is that the optimal rotation angle of the element is determined based on the second preset neural network strategy. The other processes are the same as the first search cycle operation. Similarly, this embodiment will not be repeated here.

[0085] In an exemplary embodiment, the process of determining the optimal rotation angle of the component to be optimized includes: determining the optimal rotation angle of the component to be optimized based on a second preset neural network strategy, wherein the second preset neural network strategy includes: constructing a first pin set based on all pins of the component to be optimized; for each pin in the first pin set, determining all other pins belonging to the same wire net as the pin, and constructing an associated pin set of the pin; for each pin in the first pin set, constructing a feature vector of the pin, and a feature vector of each associated pin in the associated pin set corresponding to the pin, using an attention mechanism, based on the feature vector of the pin and the feature vector of each associated pin corresponding to the pin, calculating the attention weight of each associated pin corresponding to the pin, according to the attention weight, performing weighted aggregation on the feature vectors of all associated pins corresponding to the pin to obtain a coding representation of the pin, and calculating the probability that the pin supports each candidate rotation angle based on the coding representation of the pin and the learnable vector corresponding to each candidate rotation angle; fusing the probabilities of all pins to obtain a final probability distribution of the component to be optimized adopting each candidate rotation angle; and determining the optimal rotation angle of the component to be optimized based on the final probability distribution.

[0086] The following describes a process of determining the optimal rotation angle of the component to be optimized using the second preset neural network strategy.

[0087] Second preset neural network strategy The goal is to predict the optimal rotation angle o of component j based on the current layout state s and the target component j. .

[0088] First, the pin feature is constructed, and the set of all pins of component j is recorded as For any pin , define the remaining pins belonging to the same net as the set For each , , construct its eigenvector as ;in, express and The Euclidean distance between Indicates that In the polar coordinate system constructed with the origin Relative angle (see Figure 4 ), express The area of ​​the component, Pins The type of component.

[0089] To unify the representation, the eigenvector of pin q itself is defined as ; In order to model the relative relationship between pins, this embodiment introduces an attention mechanism for each Assign attention weights: ;in, 、 、 are all learnable matrices, For collection Each pin in.

[0090] According to the above attention weights, Aggregate the adjacent pin information to obtain its encoding representation ; Calculate the orientation probability at the pin level, for each candidate rotation angle , set a learnable vector . Calculate pins Use the candidate rotation angle o probability: ;in, is a learnable matrix, For each candidate rotation angle in O.

[0091] For component-level rotation decision fusion, the decision results of all pins are averaged to obtain the rotation angle of component j using each candidate rotation angle. The final probability is as follows: .

[0092] In this embodiment, a detailed pin feature vector is first constructed, including information such as the Euclidean distance between pins, relative angles, and the area and type of the component to which they belong. These rich features enable the model to fully understand the relationships between pins and layout characteristics. By introducing an attention mechanism, the model can dynamically assign weights to each pin, thereby more accurately aggregating information about adjacent pins and obtaining an encoded representation of each pin. This attention-based aggregation method can highlight important pin relationships and avoid the shortcomings of traditional methods that treat all pins equally. Furthermore, by calculating the probability that a pin supports each candidate rotation angle and fusing the probabilities of all pins, the final probability distribution of the component adopting each candidate rotation angle is finally obtained, thereby determining the optimal rotation angle. This method not only considers the optimal rotation direction of a single pin, but also comprehensively considers the layout effect of the entire component, so that the component's rotation angle is more in line with the optimization goal of the overall layout. This embodiment can significantly improve the efficiency and quality of layout, reduce design time and labor costs, and improve the performance and reliability of the circuit board.

[0093] In an exemplary embodiment, after outputting the placement position and placement direction of each component in the last iteration as the final layout scheme of the printed circuit board, the layout method further includes: dividing all components into at least one category based on the electrical connection relationship and / or physical properties of the components; for any two components belonging to the same category, calculating the layout deviation value between the two components in the component pair, the layout deviation value includes the position deviation value and / or the rotation angle deviation value; based on the layout deviation values ​​between all component pairs belonging to the same category, calculating the neatness evaluation index of the final layout scheme.

[0094] To encourage good alignment of the layout results, this embodiment introduces a neatness reward item to quantify the consistency of the components in position and direction. The input includes , the position and rotation angle of all components and component classification labels , classification labels are used to record components Category. One feasible classification method is to classify based on the pin arrangement direction of the core component, and classify components that are on the same side as the core component pins and have a connection relationship into the same category.

[0095] The reward calculation process is as follows: First, initialize the component pair set, and set the initial set to ; for all satisfaction If the component pair , then add it to the collection ; Calculate the deviation value of each pair of components, For each pair of elements in , the deviation of their position and angle is defined as ; where the position deviation is defined as ; The angular deviation is defined as . and is a hyperparameter that controls the relative weights of position and angle deviations.

[0096] Calculating neatness reward signal .

[0097] As an optional embodiment, the neural network strategy in the first agent P Neural network strategies with R in the agent The final layout objective function value is used as the global reward to guide the two agents to jointly optimize the layout and rotation strategies.

[0098] For the first agent P and the second agent R The training process is as follows: S11: Initialization parameters, random initialization parameters and ; S12: Repeat the following process until the maximum number of iterations is reached: S121: Initialize the layout state and set the initial time step , initialize the empty layout , initialize the queue of components to be placed ; S122: Place the next component, sample the component to be placed and its position: ; S123: Update the layout and construct the components to be placed The middle layout after ; Update the queue of components to be placed: , that is, the updated queue of components to be placed From the queue Remove the components to be placed S124: Call the rotation agent to optimize the direction and call the rotation strategy Adjust the orientation of the components on the layout and record the traces: ;in, The rotation angle corresponding to the lth rotated element , is the rotated layout; S125: let , ; S126: If , then return to S122 to continue placing the next component; S127: record the complete layout track. The track recorded during the entire layout process includes: placement track: ;Rotation trajectory: ; S128: Evaluate the benefit of this trajectory based on the final layout result Calculate the objective function value , which will be used as a global reward signal for reinforcement learning. S128: Parameter update, update as follows ;renew as follows: ,in, and is the learning rate.

[0099] In summary, the present application proposes a PCB layout optimization method based on dual agents. Compared with the existing wiring algorithm based on a single agent, the present application effectively reduces the action space of each agent by introducing two agents to be responsible for the position and direction decision of the components respectively, thereby reducing the difficulty of strategy learning and improving training efficiency and stability. Whenever a component is placed, the present application can globally adjust the directions of all placed components in the layout, overcoming the limitation that the direction cannot be modified once determined in the traditional layout method, and significantly improving the global layout quality. Each agent combines heuristic strategies and neural network strategies. The heuristic strategy is used to determine the component processing order, and the neural strategy is used to decide the position or direction. The heuristic strategy for determining the component processing order can be adaptively optimized along with the neural network strategy. The present application guides the layout to be optimized in the direction of structural regularity by designing a neatness evaluation index, thereby improving the aesthetics of the layout and engineering readability.

[0100] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0101] Please refer to Figure 5 , an embodiment of the present application also provides a layout device for a printed circuit board, including: a first determination module 11, used to select a component to be placed from a set of unplaced components in the current iteration based on the layout state of the printed circuit board in the current iteration, and determine the placement position of the component to be placed on the printed circuit board; a first layout module 12, used to place the component to be placed at the placement position in a default direction and update the layout state; a second layout module 13, used to determine the optimal rotation angle of the component to be optimized for each component to be optimized in the updated layout state, rotate the component to be optimized from the current placement direction by the optimal rotation angle, obtain the preferred placement direction, and update the layout state to enter the next iteration; a layout output module 14, used to output the placement position and placement direction of each component in the last iteration as the final layout plan of the printed circuit board, and the set of unplaced components in the last iteration is empty.

[0102] In an exemplary embodiment, a process of selecting a component to be placed from a set of unplaced components in a current iteration based on a layout state of a printed circuit board in a current iteration includes: constructing a first root node using the layout state of the printed circuit board in the current iteration and the set of unplaced components as node attributes; creating at least one child node for the first root node based on at least one unplaced component in the set of unplaced components; executing a first search loop operation starting from the first root node to update the number of selections of each child node under the first root node; and when the number of executions of the first search loop operation reaches a preset number, sampling is performed in a probability distribution determined based on the number of selections of each child node under the first root node to obtain the component to be placed.

[0103] In an exemplary embodiment, the first search loop operation includes: selecting a first optimal node from all child nodes under the first root node according to the selected values ​​of each child node under the first root node in the current first search loop operation, and updating the number of visits to the first root node and the number of selections of each child node under the first root node; if the first optimal node is a leaf node, determining the placement position of the first optimal node on the printed circuit board using a first preset neural network strategy, placing the unplaced component corresponding to the first optimal node at the placement position corresponding to the first optimal node, and obtaining a first intermediate layout state; optimizing the placement direction of the components in the first intermediate layout state using a second preset heuristic strategy, and obtaining a second intermediate layout state; removing the unplaced component corresponding to the first optimal node from the set of unplaced components, and obtaining a new unplaced component. The invention relates to a method for determining a first intermediate node and a first optimal node; a first intermediate node is constructed with the second intermediate layout state and the new unplaced component set as node attributes, and the first intermediate node is added to the child node of the first optimal node; if the new unplaced component set is not empty, at least one first intermediate child node is created for the first intermediate node based on at least one unplaced component in the new unplaced component set; a placement position and placement direction of the unplaced component corresponding to the first intermediate child node on the printed circuit board are determined by using a first preset neural network strategy, a first preset heuristic strategy, and a second preset heuristic strategy; a first intermediate layout is determined based on the placement position and placement direction of each unplaced component in the unplaced component set of the current iteration, and an evaluation value of the first intermediate layout is calculated; and a selected value of each child node under the first root node is updated using the evaluation value so as to enter the next first search loop operation.

[0104] In an example embodiment, the layout device of the printed circuit board is further configured to: if the current first search loop operation is the first first search loop operation, the selected value of each child node under the first root node is 0; if the current first search loop operation is not the first first search loop operation, the selected value of each child node under the first root node is the selected value of each child node under the first root node updated based on the evaluation value in the last first search loop operation; and the process of selecting the first optimal node from all child nodes under the first root node based on the selected value of each child node under the first root node in the current first search loop operation includes: for each child node under the first root node, obtaining a decision value of the child node under the first root node based on the selected value of the child node under the first root node in the current first search loop operation and a search reward value; the search reward value is determined based on the number of visits of the first root node by the child node under the first root node in the current first search loop operation and the number of selections of the child node under the first root node; and determining the child node with the largest decision value as the first optimal node.

[0105] In an example embodiment, the process of updating the selected value of each child node under the first root node based on the evaluation value includes: determining the nodes to be updated on the search path in the current first search loop operation; for each node to be updated, obtaining the selected value of the node to be updated in the current first search loop operation based on the evaluation value, the number of visits of the node to be updated, and the selected value of the node to be updated in the current first search loop operation when the selected value of the node to be updated is not updated.

[0106] In an example embodiment, when the number of executions of the first search loop operation reaches a preset number, the process of sampling the probability distribution based on the number of selections of each child node under the first root node to obtain the component to be placed includes: when the number of executions of the first search loop operation reaches the preset number, sampling each child node under the first root node according to the obtained probability distribution after the number of selections of each child node under the first root node is transformed based on the temperature coefficient to obtain the component to be placed.

[0107] In an exemplary embodiment, the process of determining the placement position of the component to be placed on the printed circuit board includes: using a first preset neural network strategy to determine the placement position of the component to be placed on the printed circuit board, wherein the first preset neural network strategy includes: representing the layout state of the printed circuit board in the current iteration as a binary image; the pixel value of the pixel position in the binary image represents the occupancy state of the pixel position; using an image encoder to extract high-level features of the binary image to obtain a global representation vector; for each pixel position in the binary image, calculating the change in the objective function when the component to be placed is placed at the pixel position; obtaining a target change graph based on all target function changes, dividing the target change graph into several blocks, each block including multiple pixel positions; encoding each block to obtain a feature vector of the block; calculating the probability distribution of the placement position of the component to be placed based on the correlation between the global representation vector and the feature vector of each block, and the target function change corresponding to each pixel position; and determining the placement position of the component to be placed according to the probability distribution.

[0108] In an exemplary embodiment, for each element to be optimized in the updated layout state, the process of determining the optimal rotation angle of the element to be optimized includes: determining a set of unoptimized elements in the updated layout state; when the unoptimized element set is empty, outputting a rotation trajectory, the rotation trajectory including the element to be optimized selected for each rotation and the optimal rotation angle corresponding to the element to be optimized; when the unoptimized element set is not empty, selecting an unoptimized element from the unoptimized element set as the element to be optimized for the current rotation operation, determining the optimal rotation angle of the element to be optimized, removing the element to be optimized for the current rotation operation from the unoptimized element set, updating the layout state, and repeating the operation of determining the set of unoptimized elements in the updated layout state.

[0109] In an exemplary embodiment, the process of selecting a non-optimized element from a non-optimized element set as the element to be optimized for the current rotation operation includes: constructing a second root node with the layout state and the non-optimized element set corresponding to the current rotation operation as node attributes; creating at least one child node for the second root node based on at least one non-optimized element in the non-optimized element set; executing a second search loop operation starting from the second root node to update the number of selections of each child node under the second root node; when the number of executions of the second search loop operation reaches a preset number, sampling is performed in a probability distribution determined based on the number of selections of each child node under the second root node to obtain the element to be optimized for the current rotation operation.

[0110] In an exemplary embodiment, the second search loop operation includes: selecting a second optimal node from all child nodes under the second root node based on the selected values ​​of each child node under the second root node in the current second search loop operation, and updating the number of visits to the second root node and the number of selections of each child node under the second root node; if the second optimal node is a leaf node, determining an optimal rotation angle of the second optimal node on the printed circuit board using a second preset neural network strategy, adjusting the placement direction of an unoptimized component corresponding to the second optimal node at its placement position according to the optimal rotation angle of the second optimal node on the printed circuit board, to obtain a third intermediate layout state; and removing the unoptimized component corresponding to the second optimal node from the unoptimized component set to obtain a new unoptimized component set; A second intermediate node is constructed with the third intermediate layout state and the new unoptimized component set as node attributes, and the second intermediate node is added to the child node of the second optimal node; if the new unoptimized component set is not empty, at least one second intermediate child node is created for the second intermediate node based on at least one unoptimized component in the new unoptimized component set; the placement direction of the unoptimized component corresponding to the second intermediate child node on the printed circuit board is determined by a second preset neural network strategy; the second intermediate layout is determined based on the placement direction of each unoptimized component in the unoptimized component set corresponding to the current rotation operation, and a second evaluation value of the second intermediate layout is calculated; the second evaluation value is used to update the selected value of each child node under the second root node so as to enter the next second search loop operation.

[0111] In an exemplary embodiment, the process of determining the optimal rotation angle of the component to be optimized includes: determining the optimal rotation angle of the component to be optimized based on a second preset neural network strategy, wherein the second preset neural network strategy includes: constructing a first pin set based on all pins of the component to be optimized; for each pin in the first pin set, determining all other pins belonging to the same wire net as the pin, and constructing an associated pin set of the pin; for each pin in the first pin set, constructing a feature vector of the pin, and a feature vector of each associated pin in the associated pin set corresponding to the pin, using an attention mechanism, based on the feature vector of the pin and the feature vector of each associated pin corresponding to the pin, calculating the attention weight of each associated pin corresponding to the pin, according to the attention weight, performing weighted aggregation on the feature vectors of all associated pins corresponding to the pin to obtain a coding representation of the pin, and calculating the probability that the pin supports each candidate rotation angle based on the coding representation of the pin and the learnable vector corresponding to each candidate rotation angle; fusing the probabilities of all pins to obtain a final probability distribution of the component to be optimized adopting each candidate rotation angle; and determining the optimal rotation angle of the component to be optimized based on the final probability distribution.

[0112] In an exemplary embodiment, the layout device is also used to: divide all components into at least one category based on the electrical connection relationship and / or physical properties of the components; calculate the layout deviation value between the two components in the component pair consisting of any two components belonging to the same category, the layout deviation value includes the position deviation and / or the rotation angle deviation; based on the layout deviation values ​​between all component pairs belonging to the same category, calculate the neatness evaluation index of the final layout scheme.

[0113] For descriptions of features in the embodiments corresponding to the layout device for a printed circuit board, reference may be made to the descriptions of the embodiments corresponding to the layout method for a printed circuit board, which will not be described in detail here.

[0114] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps of any of the above-mentioned printed circuit board layout method embodiments.

[0115] An embodiment of the present application further provides a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps of any of the above-mentioned printed circuit board layout method embodiments when run.

[0116] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0117] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned printed circuit board layout method embodiments are implemented.

[0118] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of any of the above-mentioned printed circuit board layout method embodiments are implemented.

[0119] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0120] The above is a detailed introduction to the printed circuit board layout method, product, device, and readable storage medium provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core concept of the present application. It should be noted that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A printed circuit board layout method, characterized in that: include: Based on the layout state of the printed circuit board in the current iteration, select a component to be placed from the set of unplaced components in the current iteration, and determine a placement position of the component to be placed on the printed circuit board; Place the component to be placed at the placement position in a default direction and update the layout state; For each component to be optimized in the updated layout state, determine the optimal rotation angle of the component to be optimized, rotate the component to be optimized from the current placement orientation by the optimal rotation angle to obtain the preferred placement orientation, and update the layout state to enter the next iteration; The placement position and placement direction of each component in the last iteration are output as the final layout solution of the printed circuit board, and the set of unplaced components in the last iteration is empty.

2. The printed circuit board layout method according to claim 1, wherein: The process of selecting a component to be placed from the set of unplaced components in the current iteration based on the layout state of the printed circuit board in the current iteration includes: Constructing a first root node using the layout state of the printed circuit board of the current iteration and the set of unplaced components as node attributes; creating at least one child node for the first root node based on at least one unplaced component in the set of unplaced components; Executing a first search loop operation starting from the first root node to update the number of selections of each child node under the first root node; When the execution times of the first search loop operation reaches a preset number, sampling is performed in a probability distribution determined based on the number of selection times of each child node under the first root node to obtain a component to be placed.

3. The printed circuit board layout method according to claim 2, wherein: The first search loop operation includes: Selecting a first optimal node from among all the child nodes of the first root node according to the selected values ​​of the child nodes of the first root node in the current first search loop operation, and updating the number of visits to the first root node and the number of selections of the child nodes of the first root node; If the first optimal node is a leaf node, determining a placement position of the first optimal node on the printed circuit board using a first preset neural network strategy, and placing an unplaced component corresponding to the first optimal node at the placement position corresponding to the first optimal node to obtain a first intermediate layout state; Optimizing the placement directions of the components in the first intermediate layout state using a second preset heuristic strategy to obtain a second intermediate layout state; Eliminate the unplaced component corresponding to the first optimal node from the unplaced component set to obtain a new unplaced component set; Constructing a first intermediate node using the second intermediate layout state and the new set of unplaced components as node attributes, and adding the first intermediate node to the child nodes of the first optimal node; If the new set of unplaced components is not empty, creating at least one first intermediate child node for the first intermediate node based on at least one unplaced component in the new set of unplaced components; Determining a placement position and placement direction of the unplaced component corresponding to the first intermediate sub-node on the printed circuit board by using the first preset neural network strategy, the first preset heuristic strategy, and the second preset heuristic strategy; Determining a first intermediate layout based on the placement position and placement direction of each of the unplaced components in the unplaced component set of the current iteration, and calculating an evaluation value of the first intermediate layout; The evaluation value is used to update the selected value of each child node under the first root node, so as to enter the next first search cycle operation.

4. The printed circuit board layout method according to claim 3, wherein: Before selecting a first optimal node from among all the child nodes under the first root node according to the selected values ​​of the child nodes under the first root node in the current first search loop operation, the printed circuit board layout method further includes: If the current first search loop operation is the first first search loop operation, the selected value of the child node under the first root node is 0; If the current first search cycle operation is not the first first search cycle operation, the selected value of the child node under the first root node is the selected value updated based on the evaluation value in the previous first search cycle operation; The process of selecting a first optimal node from all child nodes under the first root node according to the selected values ​​of each child node under the first root node in the current first search loop operation includes: For each child node under the first root node, a decision value of the child node under the first root node is obtained based on the selection value of the child node under the first root node in the current first search loop operation and the search reward value; the search reward value is determined based on the number of visits to the first root node and the number of selections of the child node under the first root node that have not been updated in the current first search loop operation; The child node with the largest decision value is determined as the first optimal node.

5. The printed circuit board layout method according to claim 3, wherein: The process of updating the selected value of each child node under the first root node using the evaluation value includes: Determine the node to be updated on the search path of the current first search loop operation; For each node to be updated, based on the evaluation value, the number of visits to the node to be updated and the selected value of the node to be updated when it is not updated in the current first search cycle operation, the selected value of the node to be updated after being updated in the current first search cycle operation is obtained.

6. The printed circuit board layout method according to claim 2, wherein: When the first search loop operation is executed a preset number of times, sampling is performed in a probability distribution determined based on the number of selections of each child node under the first root node to obtain a component to be placed, including: When the execution times of the first search loop operation reaches a preset number, the selection times of each sub-node under the first root node are transformed according to the temperature coefficient, and the components to be placed are sampled from each sub-node under the first root node according to the obtained probability distribution.

7. The printed circuit board layout method according to claim 1, wherein: The process of determining the placement position of the component to be placed on the printed circuit board includes: Determine the placement position of the component to be placed on the printed circuit board using a first preset neural network strategy, wherein the first preset neural network strategy includes: Representing the layout state of the printed circuit board in the current iteration as a binary image; the pixel value of the pixel position in the binary image represents the occupancy state of the pixel position; Extract high-level features from the binary image using an image encoder to obtain a global representation vector; For each pixel position in the binary image, calculating a change in the objective function when the component to be placed is placed at the pixel position; Obtaining a target change graph based on all the target function changes, dividing the target change graph into a plurality of blocks, each block including a plurality of pixel positions; Encoding each of the image blocks to obtain a feature vector of the image block; Calculating the probability distribution of the placement positions of the components to be placed based on the correlation between the global representation vector and the feature vectors of each of the image blocks, and the change in the objective function corresponding to each pixel position; The placement position of the component to be placed is determined according to the probability distribution.

8. The printed circuit board layout method according to claim 1, wherein: For each component to be optimized in the updated layout state, the process of determining the optimal rotation angle of the component to be optimized includes: determining a set of unoptimized components in an updated layout state; When the unoptimized element set is empty, outputting a rotation trajectory, the rotation trajectory including the element to be optimized selected in each rotation and the optimal rotation angle corresponding to the element to be optimized; When the unoptimized component set is not empty, select an unoptimized component from the unoptimized component set as the component to be optimized for the current rotation operation, determine the optimal rotation angle of the component to be optimized, remove the component to be optimized for the current rotation operation from the unoptimized component set, update the layout state, and repeat the operation of determining the unoptimized component set in the updated layout state.

9. The printed circuit board layout method according to claim 8, wherein: The process of selecting an unoptimized element from the unoptimized element set as the element to be optimized for the current rotation operation includes: Construct the second root node using the layout state and unoptimized component set corresponding to the current rotation operation as node attributes; creating at least one child node for the second root node based on at least one non-optimized element in the non-optimized element set; Executing a second search loop operation starting from the second root node to update the number of selections of each child node under the second root node; When the execution times of the second search loop operation reaches a preset number, sampling is performed in a probability distribution determined based on the selection times of each child node under the second root node to obtain the element to be optimized for the current rotation operation.

10. The printed circuit board layout method according to claim 9, wherein: The second search loop operation includes: Selecting a second optimal node from among all the child nodes of the second root node according to the selected values ​​of the child nodes of the second root node in the current second search loop operation, and updating the number of visits to the second root node and the number of selections of the child nodes of the second root node; If the second optimal node is a leaf node, determining an optimal rotation angle of the second optimal node on the printed circuit board using a second preset neural network strategy, and adjusting a placement direction of an unoptimized component corresponding to the second optimal node at its placement position according to the optimal rotation angle of the second optimal node on the printed circuit board, to obtain a third intermediate layout state; Eliminating the non-optimized component corresponding to the second optimal node from the non-optimized component set to obtain a new non-optimized component set; Constructing a second intermediate node using the third intermediate layout state and the new unoptimized component set as node attributes, and adding the second intermediate node to the child nodes of the second optimal node; If the new non-optimized component set is not empty, creating at least one second intermediate child node for the second intermediate node based on at least one non-optimized component in the new non-optimized component set; Determining a placement direction of the non-optimized component corresponding to the second intermediate sub-node on the printed circuit board by using the second preset neural network strategy; determining a second intermediate layout based on the placement directions of the respective non-optimized components in the non-optimized component set corresponding to the current rotation operation, and calculating a second evaluation value of the second intermediate layout; The second evaluation value is used to update the selected value of each child node under the second root node, so as to enter the next second search cycle operation.

11. The printed circuit board layout method according to claim 8, wherein: The process of determining the optimal rotation angle of the component to be optimized includes: Determining the optimal rotation angle of the component to be optimized based on a second preset neural network strategy, wherein the second preset neural network strategy includes: Constructing a first pin set based on all pins of the component to be optimized; For each pin in the first pin set, determine all other pins that belong to the same net as the pin, and construct an associated pin set for the pin; For each pin in the first pin set, construct a feature vector for the pin and a feature vector for each associated pin in the associated pin set corresponding to the pin; utilize an attention mechanism to calculate an attention weight for each associated pin corresponding to the pin based on the feature vector of the pin and the feature vector of each associated pin corresponding to the pin; perform weighted aggregation on the feature vectors of all associated pins corresponding to the pin according to the attention weight to obtain an encoded representation of the pin; and calculate a probability that the pin supports each candidate rotation angle based on the learnable vector corresponding to the encoded representation of the pin and each candidate rotation angle; fusing the probabilities of all the pins to obtain a final probability distribution of the component to be optimized adopting each candidate rotation angle; An optimal rotation angle of the component to be optimized is determined according to the final probability distribution.

12. The printed circuit board layout method according to any one of claims 1 to 11, characterized in that: After outputting the placement positions and placement directions of the components in the last iteration as the final layout plan of the printed circuit board, the layout method further includes: Classifying all the components into at least one category based on the electrical connection relationship and / or physical properties of the components; For a component pair consisting of any two components belonging to the same category, calculating a layout deviation value between the two components in the component pair, the layout deviation value including a position deviation value and / or a rotation angle deviation value; Based on the layout deviation values ​​between all pairs of components belonging to the same category, a neatness evaluation index of the final layout solution is calculated.

13. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the steps of the printed circuit board layout method according to any one of claims 1 to 12 are implemented.

14. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the printed circuit board layout method according to any one of claims 1 to 12 when executing the computer program.

15. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the printed circuit board layout method according to any one of claims 1 to 12 are implemented.

Images