680 results about "Circuit graph" patented technology

A multi-layer circuit board formed by laminating a plurality of circuit boards each having lands arranged in many number in the form of a lattice or in a staggering manner on the side of the mounting surface and having circuit patterns with the ends on one side thereof being connected to said lands and with the ends on the other side thereof being drawn toward the outside from a region where said lands are arranged; wherein the lands for drawing the circuit patterns in a number not less than a+1 are arranged on the oblique lines of an isosceles triangle having a base formed by consecutive lands of a number of n and having oblique lines in the diagonal directions, the value n satisfying m>=k+1 of the two values of:wherein "a" is the number of the circuit patterns that can be arranged between the neighboring lands on the circuit board, and "n" is a parameter.

The invention discloses a manufacturing method of a high-order multistage HDI (High Density Interconnection) printed circuit board. An expansion coefficient of a cross-band veneer is pre-compensated according to a layer number, a dead hole stacking number and an engineering pre-designed lamination structure of a product, a press frequency and a material characteristic; a reference target coordinate, a shape, a size, a process aligning manner and the like are aligned for design demands for systematizing different graph levels and production positioning reference points, so that the alignment matching index and the expansion alignment precision among different levels and different components can be achieved; all the alignment problems caused by various factors in a production process of a three-stage HDI printing circuit can be considered; the alignment problems among a series of important PCB (Printed Circuit Board) processes, such as an inner layer graph, a secondary outer layer circuit, a secondary outer layer buried hole, an outer layer circuit, a mechanical through hole, a radiation dead hole and solder resistance of a one-stage HDI product, a two-stage HDI product and a three-stage HDI product, can be solved; and meanwhile, the hole overlapping precision of micro dead holes and the alignment precision matching indexes of the dead holes, the through hole and a circuit graph can be ensured.

A media case and a circuit pattern sheet with a simple configuration is provided that allows highly dense collection and reliable recognition of housed disk media.

The media case 1 can house disk media 50 provided with an RFID tag (not illustrated in the drawing). This media case 1 includes an antenna element 51a being formed on its back plane to exchange an electromagnetic wave signal with the outside of the media case 1; a waveguide line 52a formed in the vicinity of its center therethrough along the disk media 50 from the antenna element 51a to guide high-frequency signals representing the electromagnetic wave signals to the antenna element 51a; and a resonance element 53a being formed adjacent to this waveguide line 52a and electromagnetically induced by the high-frequency signal.

A self-assembly method for circuit patterns includes generating a set of tiles, each of the tiles corresponding to a segment of molecules, the set of tiles comprising a set of rule tiles and a set of boundary tiles, each tile having one or more binding regions; assigning a label from a set of labels to each binding region; self interacting, with attractive forces, one or more of the tiles with one or more other tiles among the set of tiles; associating using selective interaction of at least one boundary tile from the set of boundary tiles with at least one rules tile from the set of rules tiles based upon at least a label from the one boundary tile and at label from the one rules tiles; and bonding at least one binding region of the one boundary tile with at least one binding region of the one rules tile.

A stacked integrated circuit package and a method for manufacturing the same are provided.

The stacked integrated circuit package includes a first integrated circuit package comprising a first substrate, a first semiconductor chip, and a first molding portion, an interposer mounted on the first substrate to be electrically connected to the circuit pattern of the first substrate by a first solder bump, the interposer being provided with an opening to accommodate the first semiconductor chip, and a second integrated circuit package stacked on the first integrated circuit package and the interposer and electrically connected to the interposer by a second solder bump, the second integrated circuit package comprising a second substrate, a second semiconductor chip, and a second molding portion.

The invention relates to the printed circuit board technology field, especially relating to a processing method of a second-order ladder groove bottom graphical printed board. The method comprises the following steps: carrying out a pretreatment on a first daughter board which reserves a plug-in hole, a second daughter board provided with a circuit graph and a third daughter board provided with a circuit graph; pressing the first daughter board and the second daughter board to obtain a first motherboard; carrying out distressing, hole drilling, copper deposition, internal layer figure transfer, and etching resistance metal protective layer plating treatments on the first motherboard to obtain a second motherboard; pressing the third daughter board and the second motherboard to obtain a third motherboard; carrying out distressing, hole drilling, copper deposition, external layer figure transfer treatments on the third motherboard to obtain a finished second-order ladder groove bottom graphical printed board. According to the second-order ladder groove bottom graphical printed board prepared by the method, each ladder can be subjected to wiring and plug-in installation, and a usage scope of a plate is expanded. The invention also relates to the second-order ladder groove bottom graphical printed board.

The invention relates to a ceramic surface modifying technology, particularly relates to a method for metalizing the surface of a ceramic profiled bar, and specifically provides a preparation method of a ceramic circuit board... The preparation method of the ceramic circuit board comprises the preparation steps of: (1) preparing a ceramic substrate; (2) engraving a required circuit pattern with laser on the surface of the ceramic substrate; (3) in chemical plating, and chemically plating copper on the ceramic substrate obtained in the step (2) to realize bottoming; and (4) chemically plating nickel or chemically plating gold or silver on the surface of a plated layer, so as to prevent copper from being oxidized. According to the preparation method of the ceramic circuit board provided by the invention, a laser engraving technology is combined with chemical copper plating, so that the ceramic board is selectively coated with copper, and the good selectivity is achieved. By using the laser engraving technology, the binding force of a conductive layer with a ceramic base body is good; production equipment is cheap and easy to obtain. Furthermore, the three-dimensional ceramic circuit board can be easily produced; the circuit pattern design is very simple; and the circuit precision is high. Moreover, compared with the other technologies, the preparation method provided by the invention has the advantage that the 'three wastes' emission in a production process is reduced.

A dummy filling method for a semiconductor manufacturing process provides a circuit pattern and generates a density report of the circuit pattern to identify a feasible area for dummy insertion. The method also includes using the density report to simulate a planarization manufacturing process and identifying hot spots on the circuit pattern, filling virtual redundant patterns in the feasible area, and then adjusting the density report. The method simulates the planarization process using the adjusted density report until the hot spot is removed. The invention can reduce the amount of redundant metal in circuit design and save photomask time, CPU time, and signal storage memory. This will help design timing closure (time closure) faster and easier.

A method for fabricating an organic circuit board having embedded passive components, such as resistors, capacitors and inductors, is disclosed. In embedding a resistor or capacitor, a passive unit of a resistive film or a capacitive film is first made on one side of a conductive foil. In forming an inductor, a soft magnetic film is first made on one side of a conductive foil. The foil with the soft magnetic film is then introduced into the multilayer circuit board processing. The electrodes for various passive components or spiral coils for the inductive components and electrical circuit pattern are finally made on the same conductive foil simultaneously. The soft magnetic film deposited on the top of the spiral coil may be made to further improve inductor performance.

The invention discloses a flow diagram of a PCB electroplating method for improving the electroplating uniformity. The PCB electroplating method for improving the electroplating uniformity comprises the steps that firstly, an auxiliary copper block is additionally arranged on a PCB when the PCB is designed; then the PCB is manufactured and etched according to the normal parameters and process; then secondary dry film manufacturing is carried out on the etched PCB, namely all areas, except the area where the copper block is additionally arranged, of the PCB are covered with a dry film photoresist, and the copper block is exposed; the exposed copper block is removed through etching by means of a negative film etching method, and a final circuit graph is formed; the PCB where the final circuit graph is formed is processed according to an existing technological process until a finished product is obtained. By the adoption of the PCB electroplating method for improving the electroplating uniformity, the problem that electroplating and etching are difficult due to the uneven electroplating of a PCB with graphs distributed in an isolated mode is solved, the uniformity of the thickness of electroplating copper of the PCB is improved, and therefore signals can be transmitted more accurately when a user uses the PCB.

The invention relates to the field of circuit board manufacture, specifically a method for manufacturing a large-size precise circuit board. The method employs a mode of two-time exposure, and avoids a problem that a line width of a formed circuit graph is reduced because a height difference at a jointing overlapping part of two films enables the attaching with a plate to be untight. The width of an overlapped region is set as 0.2 mm, and the circuit graph, corresponding to the overlapping region, on the second circuit film is enabled to be 0.05 mm greater than a to-be-manufactured circuit graph, thereby guaranteeing that circuit graphs which are formed in the overlapping region during the first exposure and the second exposure are accurately aligned, and avoiding problems that the exposure of a circuit graph in the overlapped region is poor and the alignment is deflected. The method not only can be used for manufacturing a precise circuit board with a line distance being less than 0.1 mm, but also can be used for manufacturing a circuit board with the length being greater than 914 mm.

The invention discloses a manufacturing method for a flexible and hard combined thin PCB, and is characterized by comprising the steps as follows: a) a flexible board with a circuit graphs on the surface thereof is provided; b) a protective film is arranged on the surface of the flexible board provided with the circuit graphs; c) prepregs with windows are provided, the prepregs are stacked on the surface of the flexible plate, and the protective film corresponds to the position of the windows of the pregregs; d) hard boards are provided and stacked on the surfaces of the prepregs, and the prepregs are located among the flexible board and the hard boards; e) the laminating is carried out; and f) the parts of the hard boards corresponding to the position of the protective film are removed. The invention has the benefits that a first hard board and a second hard board located on the most outer layers of the thin PCB can only adopt copper foil, and the problem that an etching solution provided by the copper foil damages the circuit graphs on the flexible board is solved, so that the manufacturing of thinner PCBs is achieved; and after manufacturing the flexible plate, a protective layer is not required before manufacturing the flexible and hard combined thin PCB, and the procedure of the manufacturing is simplified.

A light emitting diode package structure includes a substrate (10), LED bare chips (20) and a lens (30). The substrate (10) has an upper surface (11), a lower surface (12) and a side surface (13) between the upper surface (11) and the lower surface (12). The upper surface (11) is provided with a circuit pattern (111). The side surface (13) is provided with a groove (131). The LED bare chips (20) are fixed on the upper surface (11) and electrically connected with the circuit pattern (111). The lens (30) covers the LED bare chips (20), the upper surface (11) and the circuit pattern (111) by an injection molding process so as to be inserted into the groove (131). With this arrangement, the connecting strength between the substrate (10) and the lens (30) can be enhanced, thereby achieving waterproof and anti-electrostatic effects. Further, material cost of the present invention is reduced greatly.

The invention relates to a circuit board manufacturing method, which comprises the following steps: a copper-clad substrate is provided, wherein the copper-clad substrate is provided with a molding area and an edge area surrounding the molding area; at least one group of counterpoint marks are formed at the edge area of the copper-clad substrate, wherein each group of counterpoint marks include a plurality of marks distributed crisscross; a photoresist layer is formed on the copper-clad substrate; a photomask is provided, wherein the photomask is provided with at least one cross counterpoint pattern corresponding to at least one group of counterpoint marks; counterpoint is carried out on the photomask and the copper-clad substrate by an optical counterpoint device so as to make at least one cross pattern of the photomask respectively cover at least one group of counterpoint marks of the copper-clad substrate; the photoresist layer is exposed; the photoresist layer is developed; and the copper-clad substrate is etched so as to form a circuit graph on the molding area.

The invention discloses a method for detecting layer-to-layer registration of circuit graphs at the two surfaces of a core board, which is used for improving the detecting precision of layer-to-layer registration of the circuit graphs at the two surfaces of the core board of the existing printed circuit board. The method comprises the following steps: graphic data is respectively drawn on a firstsurface and a second surface of the core board of the printed circuit board, wherein the same positions of the graphic data of the first surface and the second surface are respectively drawn with a detecting graph, the core board is manufactured according to the graphic data of the first surface and the second surface on which the detecting graphs are drawn, wherein the manufactured core board comprises a detected object corresponding to the position of each detecting graph, a positioning structure is formed on a set position of the manufactured core board; and the layer-to-layer offset of the circuit graphs at the two surfaces of the core board is determined according to the measured distance from the detected objects on the first surface and the second surface of the core board to the positioning structure. The invention also discloses a printed circuit board and a device for detecting layer-to-layer registration of circuit graphs at the two surfaces of the core board.

An electric junction box that can accommodate various circuit patterns in accordance with a combination of a printed-circuit board and a case housing the printed-circuit board. Connection pins connected to conductors are provided in a projecting position at intervals along the peripheral edge of a printed-circuit board. An opening corresponding to the printed-circuit board is formed in a central region of the upper side of a case. Connector joints are positioned on the peripheral walls of the four sides of the case, and L-shaped terminals are provided at the same intervals as for the connection pins along the opening. Additionally, a connection structure of a tuning-fork terminal includes a tuning-fork terminal at the end portion of a conducting plate base bent vertically and having a press connection slot in the center of the vertical portion; and a tab-shaped mating terminal electrically connected to contact portions projecting from inner sides of the slot.