367 results about "Circuit graph" patented technology

The invention relates to the field of image defect detection, in particular to an SMT defect detection method and system based on image recognition, and the method comprises the steps: shooting a to-be-detected circuit board through an optical detection device to obtain an original circuit image, carrying out the illumination compensation of the original circuit image to obtain a target circuit image, carrying out the two-dimensional wavelet decomposition of the target circuit image, and carrying out the detection of the SMT defect. The method comprises the steps of obtaining a horizontal component floating-point diagram and a vertical component floating-point diagram, performing edge identification on a target circuit image according to the horizontal component floating-point diagram and the vertical component floating-point diagram to obtain an edge pixel point set, clustering the edge pixel point set by using the number of elements to obtain a plurality of element edge point sets, and constructing a plurality of surface-mounted component areas based on the plurality of component edge point sets, determining a defect component area group in the plurality of surface-mounted component areas, and transmitting the defect component area group to a display device. According to the invention, the accuracy of SMT mounting defect detection can be improved, and the defect response speed of a production line is improved.

A printed circuit board according to an embodiment comprises: an insulating layer; a circuit pattern disposed on the upper surface of the insulating layer; a support layer which is disposed on the upper surface of the insulating layer to expose the upper surface of the circuit pattern and is in contact with the sides of the circuit pattern; and a protective layer disposed on the upper surfaces of the support layer and the circuit pattern, wherein the upper region of the insulating layer comprises a first region and a second region, and the protective layer comprises an open region exposing the upper surfaces of the support layer and the circuit pattern that are disposed in the first region, and the support layer comprises a first upper surface positioned at the highest level among the upper surfaces of the support layer and a second upper surface positioned at the lowest level among the upper surfaces of the support layer, the second upper surface being lower than the first upper surface, and the protective layer comprises a first portion which contacts the upper surface of the circuit pattern of the first region and a second portion which contacts the upper surface of the support layer of the first region, and the second portion of the protective layer contacts the second upper surface of the support layer and includes a first lower surface which is lower than the upper surface of the circuit pattern.

The invention discloses a novel automobile back view mirror flexible printed circuit board prepared based on weldable silver paste, and belongs to the technical field of electronic materials and devices, conductor patterns in the flexible printed circuit board comprise a main circuit pattern and an auxiliary function structure formed by weldable low-temperature curing silver paste; the curing temperature of the weldable low-temperature silver paste is 125-135 DEG C, and the weldable low-temperature silver paste comprises conductive filler, a polymer resin system, a high-boiling-point ester solvent, a curing agent, a silane coupling agent, a polyamide wax thixotropic agent, a polysiloxane defoaming agent, modified carbon nanotubes, modified aluminum oxide powder, modified barium sulfate and a low-stress modifier. The polymer resin system comprises novolac epoxy resin, biphenyl epoxy resin and a polyacrylate-CTBN copolymer; through the synergistic effect of all the components and an innovative process, comprehensive improvement of mechanical reliability, environmental durability, conductive stability and power load capacity is achieved, and the strict requirement for high reliability of the automobile rearview mirror in an extreme environment is perfectly met.

The invention discloses a novel notebook flexible printed circuit board prepared based on weldable low-temperature silver paste and a backlight module, and belongs to the technical field of electronic materials and devices. Conductor patterns of the flexible printed circuit board comprise a main circuit pattern formed by rolled copper; the auxiliary function structure is formed in a local area of the main circuit pattern by weldable low-temperature silver paste; the curing temperature of the weldable low-temperature silver paste is 130-145 DEG C, the weldable low-temperature silver paste comprises conductive filler, a polymer resin system, an ester solvent, a curing agent, a silane coupling agent, a polyamide wax thixotropic agent, a polysiloxane defoaming agent, modified carbon nanotubes and modified antimony tin oxide powder, and the conductive filler comprises flaky silver powder, spherical silver powder and low-temperature alloy powder. The low-temperature alloy powder is Sn42Bi58 low-temperature alloy powder of which D50 is 12 [mu] m-15 [mu] m; according to the invention, low-temperature curing, high flexibility, excellent conductivity and direct weldability are integrated, and a solution suitable for local repair of a flexible printed circuit board and direct mounting of a jumper and a Mini LED chip is provided.

A method and corresponding apparatus train a circuit topology generator. The method transforms a training circuit topology into a hierarchical graph in a high-dimensional data space. Nodes of the hierarchical graph correspond to selected subgraphs forming a subgraph basis. The selected subgraphs represent circuit elements of the topology. The method converts the hierarchical graph into a directed acyclic graph (DAG) to be processed by a circuit graph neural network (CktGNN) into a latent space. The latent space is a lower-dimensional data space relative to the high-dimensional data space. The method transforms the DAG into an estimated circuit topology via the circuit topology generator and trains the CktGNN and circuit topology generator based on differences between the training circuit topology and estimated circuit topology toward causing the circuit topology generator to converge on the training circuit topology. The trained circuit topology generator may be employed to generate novel circuit topologies, automatically.

The invention relates to the field of artificial intelligence, natural language processing and electronic design automation, in particular to a circuit analysis generation and modification method based on form and logic separation, comprising the following steps: step 1, a complete circuit generation process; 2, separating and analyzing logic and form; step 3, intelligently modifying an operator; and step 4, labeling-generating-modifying a system: step 1, converting a natural language to a DSL code, then converting the DSL code into a logic diagram structure, and finally generating a morphological layout and a complete circuit diagram. According to the method, a complete process from a natural language to DSL, a logic diagram, morphological layout and a final circuit is achieved, the intelligent degree of circuit analysis is improved, through morphological and logic decoupling, the generalization ability of circuit analysis is improved, the complete automatic process from natural language description to final circuit generation is achieved, meanwhile, efficient circuit modification and optimization are supported, and the method is suitable for popularization and application. The method also provides a modification operator, supports accurate circuit adjustment, and improves the design efficiency.

According to the present invention, a semiconductor package is provided. A semiconductor package may include a package substrate, and a first semiconductor chip disposed on the package substrate, wherein the first semiconductor chip may include a semiconductor substrate including a first surface and a second surface opposite to the first surface, a circuit pattern region disposed on the first surface of the semiconductor substrate and including a plurality of circuit patterns, a signal wiring layer disposed on the circuit pattern region and electrically connected to the plurality of circuit patterns, and a power wiring layer disposed on the second surface of the semiconductor substrate and electrically connected to the plurality of circuit patterns through a plurality of through vias extending through the semiconductor substrate, and the package substrate may include a signal transmission pattern electrically connected to the signal wiring layer of the first semiconductor chip, and a power transmission pattern electrically connected to the power wiring layer of the first semiconductor chip.

A circuit board including a first insulating layer; a first circuit pattern disposed on the first insulating layer; and a second insulating layer disposed on the first insulating layer and including a cavity. An upper surface of the first insulating layer includes a first region that does not vertically overlap the cavity; a second region vertically overlapping the cavity; and a boundary region between the first region and the second region. The first circuit pattern includes a first-first circuit pattern disposed on the boundary region of the first insulating layer. The first-first circuit pattern includes a first portion that does not vertically overlap the cavity, and a second portion connected to the first portion and vertically overlapping the cavity. A thickness of the first portion of the first-first circuit pattern is different from a thickness of the second portion of the first-first circuit pattern.

The invention belongs to the field of PCB production, and particularly relates to a production method for controlling galvanic effect generation at a PAD of a PCB, and the production method comprises the following steps: S1, manufacturing design graphic data of the PCB, and designing joints of a circuit and a square PAD and a circular PAD to be teardrop-shaped; s2, cutting the substrate into a specified size according to design graphic data, and cleaning a surface plate; s3, converting a Gerber file in the design graphic data into a film negative, and transferring a circuit pattern to a substrate copper foil coated with photosensitive resin through an exposure machine; s4, removing the unexposed photosensitive resin by using a developing solution; when image data is manufactured and designed, the connecting position of the circuit and the PAD is designed to be in a teardrop shape, after follow-up transfer printing etching, a teardrop-shaped structure is formed at the connecting position of the circuit and the PAD in the conductive circuit, the connecting area between the circuit and a bonding pad is effectively increased, and the risk that the connecting position of the circuit and the PAD is disconnected due to corrosion of a severe environment in follow-up production and use is reduced.

Methods, systems, and computer-readable media are used in graph-based machine learning of analog integrated circuits (ICs). In a first aspect, functional device pairs in transistor-level circuits are detected and classified using a hybrid approach combining a subgraph isomorphism algorithm, such as VF2, with a trained relational-graph convolutional network (RGCN). The VF2 algorithm identifies candidate pairs and initial categories, while the RGCN filters false positives using link prediction scores, preserving category labels for validated pairs. In a second aspect, a relational GraphSAGE model performs multi-class link prediction on a heterogeneous graph with netlist and functional relation edge types, labeling device pairs into analog primitive categories without technology-dependent features and merging overlapping pairs into larger functional groups. In a third aspect, circuit performance is predicted using a hierarchy-aware graph neural network comprising an edge-conditioned convolution (ECC) layer and multiple Circuit graph isomorphism network layers corresponding to hierarchy levels of device groupings.

A flexible printed circuit board according to an embodiment includes: a substrate; and a circuit pattern disposed on the substrate, wherein the circuit pattern includes a plurality of first circuit patterns, a plurality of second circuit patterns, and a plurality of third circuit patterns, wherein the third circuit pattern includes a third-first pad portion, a third-second pad portion, and a third wiring portion connecting the third-first pad portion and the third-second pad portion, a plurality of fourth wiring portions are disposed between a plurality of third wiring portions, a line width of the third wiring portion is greater than a line width of the fourth wiring portion, and a distance between the third wiring portion and the fourth wiring portion adjacent to the third wiring portion is greater than a distance between the fourth wiring portions.

According to one embodiment of the present disclosure, there is provided a phase conversion device including: at least one base portion provided to extend in a longitudinal direction and having a first circuit pattern formed on one surface; a pair of ground walls extending from both lateral sides of each of the at least one base portion in a direction parallel to a height direction perpendicular to the at least one base portion; a pair of pattern walls provided so as to protrude from one surface of each of the at least one base portion in a direction parallel to the height direction, at least one surface of each of the pair of pattern walls having a second circuit pattern formed thereon, the second circuit pattern being electrically connected to the first circuit pattern; and a pair of dielectrics provided to be movable in a direction parallel to the longitudinal direction, at least a portion of each of the pair of dielectrics being disposed between each of the pair of ground walls and each of the pair of pattern walls.

The application discloses a novel flexible printed circuit board and camera module prepared based on weldable low-temperature silver paste, and belongs to the technical field of electronic materials and devices. The conductor pattern in the flexible printed circuit board comprises a main circuit pattern and an auxiliary function structure formed by weldable low-temperature cured silver paste. The curing temperature of the weldable low-temperature silver paste is 87-103 DEG C. The silver paste comprises conductive fillers, a polymer resin system, ester solvents, a curing agent, a silane coupling agent, polyamide wax thixotropic agents, polysiloxane defoaming agents, modified carbon nanotubes, modified antimony tin oxide powder, modified ceramic fillers and low-stress modifiers. The polymer resin system comprises hydrogenated bisphenol A type epoxy resin, diphenyl type epoxy resin and polyacrylate-CTBN copolymer. The conductive fillers comprise silver-coated copper flaky powder, nano silver wire and low-temperature alloy powder. Through the synergistic effect of components and the innovative process, the comprehensive improvement of mechanical properties, conductive properties, high-frequency characteristics and welding reliability is realized under the premise of ultralow-temperature curing.

The invention belongs to the technical field of graphene, and particularly relates to graphene leather capable of realizing temperature-sensitive color development and a preparation method of the graphene leather. As the graphene heating functional layer adopts the high-thixotropic silver paste, the printed circuit pattern is clear in edge, uniform in thickness and extremely high in consistency with the designed pattern; and a clear interface is formed between a silver paste circuit and leather fibers, and improper penetration is avoided. And the circuit resistance value consistency is excellent (the deviation is controlled within + / -5%), so that rapid, uniform and stable planar heating can be realized after the graphene heating layer is connected, and the local overheating hidden danger is perfectly eliminated. According to the present invention, the natural texture and the soft touch feeling of the leather are maintained while the efficient and safe heating performance with the visual color developing function is achieved.

The application discloses a method and device for feature extraction of integrated circuit layouts and a non-transitory computer readable storage medium thereof. A circuit pattern layout file to be implemented on a semiconductor wafer is obtained from a memory. Data preparation and preprocessing is performed on the circuit pattern layout file. A deep learning model is established and trained. Transfer learning and model fusion are performed on the deep learning model. The deep learning model is used to perform image segmentation and feature extraction on the circuit pattern layout file to extract a plurality of features. Density parameters and total perimeter parameters of the plurality of features are calculated.

This invention relates to a method for manufacturing a multilayer printed circuit board, comprising: a step of preparing a first circuit board; a step of preparing a metal laminate; a step of stacking the first circuit board on both sides of a carrier film to form a first multilayer laminate; a step of stacking the metal laminate on both sides of the first multilayer laminate to form a second multilayer laminate; a step of hot-pressing the second multilayer laminate; a step of forming a second circuit pattern on the metal foil of the hot-pressed second multilayer laminate to form a third multilayer laminate; and a step of separating the carrier film and the first circuit board from the third multilayer laminate to obtain two multilayer printed circuit boards having the first circuit board and the second circuit board stacked on them, respectively, and adjusting the MFR of the dried film to be greater than the MFR of the first thermoplastic resin layer.

A circuit board according to an embodiment includes: an insulating layer including first to third regions; an outer layer circuit pattern disposed on upper surfaces of the first to third regions of the insulating layer; and a solder resist including a first portion disposed in the first region of the insulating layer, a second portion disposed in the second region, and a third portion disposed in the third region, wherein the outer layer circuit pattern has a first height, the third portion of the solder resist is disposed on an upper surface of the outer layer circuit pattern to have a second height, the first region includes a first sub-region and a second sub-region, the first portion includes a first sub-portion disposed in the first sub-region and a second sub-portion disposed in the second sub-region, an upper surface of the first sub-portion is positioned higher than the upper surface of the outer layer circuit pattern and lower than an upper surface of the third portion, an upper surface of the second sub-portion is positioned lower than the upper surface of the outer layer circuit pattern, and a surface roughness of the third portion of the solder resist is different from a surface roughness of the first portion of the solder resist.

A flexible circuit board includes a substrate, a plurality of circuit patterns disposed on the substrate, and a protective layer disposed on the circuit patterns, wherein each of the plurality of circuit patterns has a thickness greater than 8 µm and less than or equal to 25 µm, and wherein a thickness deviation between the plurality of circuit patterns is 0.5 µm to 3 µm. When the flexible circuit board is connected with a display panel, the display panel can have high performance and high current can flow through the display panel. The circuit pattern having the features according to the present invention is prevented from being damaged by high current.

The purpose of the present invention is to provide a photosensitive conductive paste which makes it possible to form a high-resolution circuit pattern and exhibits low shrinkage when sintering the circuit pattern.　The present invention is a photosensitive conductive paste which contains a conductive powder (A) and a photosensitive organic component (B), wherein the median size r of the particle diameter distribution of the conductive powder (A) is 3.0-6.0μm, inclusive, and the content V1 of the conductive powder (A) constitutes 37-55 vol%, inclusive, of the solid content overall.

The invention relates to a sensor for determining two measured variables of a gas. The sensor has at least a first sensor element and a second sensor element and two control connections. The first sensing element and the second sensing element are connected in series. The sensor element is arranged between the actuation connections. The first sensing element is provided with a first electronic equivalent circuit diagram, and the first electronic equivalent circuit diagram comprises a parallel circuit composed of a first resistor and a first capacitor. The second sensing element is provided with a second electronic equivalent circuit diagram, and the second electronic equivalent circuit diagram comprises a second capacitor.

A method for making an integrated circuit (IC) includes inserting black boxes into a layout of the IC; connecting the black boxes with a connectivity network; and inserting first dummy patterns in areas of the layout outside of the black boxes and the connectivity network. After the inserting of the first dummy patterns, the method further includes replacing the black boxes with circuit macros that have one-to-one correspondence with the black boxes, wherein each of the circuit macros includes circuit patterns in a central area of the respective circuit macro and second dummy patterns surrounding the central area. In the method, at least one of the following operations is performed by an electronic design automation (EDA) tool: the inserting of the black boxes, the connecting of the black boxes, the inserting of the first dummy patterns, and the replacing of the black boxes with the circuit macros.

The invention is applicable to the technical field of electronic design automation, and provides a cross-design software netlist data co-processing method, which comprises the following steps: acquiring first netlist data; wherein the first netlist data is used for representing a logic connection relationship among a plurality of electrical components in the first schematic diagram, packaging library information corresponding to the electrical components and the like; wherein the first schematic diagram is a schematic diagram constructed based on first design software; performing data format conversion on the first netlist data to obtain second netlist data; importing the second netlist data into second design software; wherein the second design software is different from the first design software; and generating a circuit diagram corresponding to the printed circuit board based on the second netlist data and the second design software. According to the method, when cross-software circuit diagram design is carried out, an engineer does not need to consume extra time in format adaptation and data verification, so that the method focuses on core design links such as circuit diagram layout and wiring, the design period is shortened on the whole, and the working efficiency is improved.

The present disclosure relates to a method of debugging a printed circuit board having at least one boundary-scan compliant device, the method using an electronic processing unit and comprising the steps of: retrieving boundary-scan properties of the at least one boundary-scan compliant device, the boundary-scan compliant device comprising a list of boundary-scan compliant circuit terminals of the at least one boundary-scan compliant device; selecting and displaying a circuit diagram of at least a portion of the device mounted on the printed circuit board, the circuit diagram comprising at least one device of a plurality of devices mounted on the printed circuit board and at least one other device of the plurality of devices, the other device comprising circuit terminals that are interconnected with circuit terminals of the device for visualizing at least the device, the other device and the interconnections. The present disclosure also relates to a corresponding debugging apparatus and to a corresponding computer program product.

A circuit board according to an embodiment includes: a first circuit layer; a first insulating layer disposed on the first circuit layer; a second circuit layer disposed on the first insulating layer; and a second insulating layer disposed on the second circuit layer, wherein the first circuit layer includes a first circuit pattern disposed along a peripheral direction of an outer side surface of the first insulating layer at a position closest to the outer side surface of the first insulating layer, wherein the second circuit layer includes a second circuit pattern disposed along a peripheral direction of an outer side surface of the second insulating layer at a position closest to the outer side surface of the second insulating layer, and wherein a first separation distance in a horizontal direction from the outer side surface of the first insulating layer to the first circuit pattern is different from a second separation distance in the horizontal direction from the outer side surface of the second insulating layer to the second circuit pattern.

A wafer structure includes a substrate, a scribe line, a chip circuit pattern, and a peripheral metal pattern. The scribe line defines a chip unit on the substrate. The chip circuit pattern is disposed in a central region of the chip unit. The peripheral metal pattern is disposed in a peripheral region of the chip unit surrounding the central region. The peripheral metal pattern includes a seal ring pattern surrounding the central region and an alignment pattern disposed between the scribe line and the seal ring pattern.

To provide a composite metal foil in which a second copper layer is laminated on a nickel layer and which can be suitably used for a printed wiring board because a circuit can be formed by selective etching, the contrast between different kinds of metals is clear and can be easily identified, and erroneous detection and detection omission of a circuit pattern in image inspection and displacement in the case of multilayering hardly occur.SOLUTION: A composite metal foil comprising at least one layer structure of a first copper layer / a nickel layer / a second copper layer, wherein an absolute value of a difference between a lightness L * Cu value of a surface of the second copper layer and a lightness L * Ni value of a surface of the nickel layer on which the second copper layer is laminated is 15 or more.SELECTED DRAWING: Figure 1

A circuit board including an insulating layer including a first region and a second region; a plurality of outer layer circuit patterns disposed on upper surfaces of the first region and the second region of the insulating layer; and a solder resist including a first part disposed on the first region of the insulating layer and a second part disposed on the second region of the insulating layer. The first part includes an upper surface having a curved surface and exposes an upper surface of an outer layer circuit pattern disposed on the first region of the insulating layer. The second part covers an upper surface of an outer layer circuit pattern disposed on the second region of the insulating layer, and at least a part of the upper surface of the first part is positioned lower than the upper surface of the outer layer circuit pattern.

An object is to provide a technique capable of reducing stress in the entire semiconductor device. The semiconductor device includes a plurality of sub-modules including a first sealing member, an insulating substrate provided with a first circuit pattern electrically connected to at least one of the conductive plates of the plurality of sub-modules, connection members electrically connected to at least one of the conductive pieces of the plurality of sub-modules, and a second sealing member having lower hardness than the first sealing member, which seals the plurality of sub-modules, the insulating substrate, and the connection members.

Provided are: a conductive silver particle layer which does not undergo deterioration in conductivity due to damage in a micro-etching step, has high adhesion between a substrate and a circuit pattern, has little undercut, and has excellent design reproducibility; a method for manufacturing a laminate electrically connected to a circuit pattern capable of forming a wiring having a satisfactory rectangular cross-sectional shape as both surfaces or an inner layer of a circuit wiring, a method for manufacturing a circuit board, a printed wiring board, a package substrate, an interposer, and an electromagnetic wave shielding film. A method for producing a laminate in which a resin layer (B), a conductive plating base layer (C) containing a conductive substance (c2) and a dispersant (c1), and a copper layer (D) are laminated in this order on at least one surface of a support (A), the method having a step for selectively removing the copper layer (D) using an etching solution.