200 results about "Circuit graph" patented technology

The invention belongs to the field of PCB production, and particularly relates to a production method for controlling galvanic effect generation at a PAD of a PCB, and the production method comprises the following steps: S1, manufacturing design graphic data of the PCB, and designing joints of a circuit and a square PAD and a circular PAD to be teardrop-shaped; s2, cutting the substrate into a specified size according to design graphic data, and cleaning a surface plate; s3, converting a Gerber file in the design graphic data into a film negative, and transferring a circuit pattern to a substrate copper foil coated with photosensitive resin through an exposure machine; s4, removing the unexposed photosensitive resin by using a developing solution; when image data is manufactured and designed, the connecting position of the circuit and the PAD is designed to be in a teardrop shape, after follow-up transfer printing etching, a teardrop-shaped structure is formed at the connecting position of the circuit and the PAD in the conductive circuit, the connecting area between the circuit and a bonding pad is effectively increased, and the risk that the connecting position of the circuit and the PAD is disconnected due to corrosion of a severe environment in follow-up production and use is reduced.

Methods, systems, and computer-readable media are used in graph-based machine learning of analog integrated circuits (ICs). In a first aspect, functional device pairs in transistor-level circuits are detected and classified using a hybrid approach combining a subgraph isomorphism algorithm, such as VF2, with a trained relational-graph convolutional network (RGCN). The VF2 algorithm identifies candidate pairs and initial categories, while the RGCN filters false positives using link prediction scores, preserving category labels for validated pairs. In a second aspect, a relational GraphSAGE model performs multi-class link prediction on a heterogeneous graph with netlist and functional relation edge types, labeling device pairs into analog primitive categories without technology-dependent features and merging overlapping pairs into larger functional groups. In a third aspect, circuit performance is predicted using a hierarchy-aware graph neural network comprising an edge-conditioned convolution (ECC) layer and multiple Circuit graph isomorphism network layers corresponding to hierarchy levels of device groupings.

A flexible printed circuit board according to an embodiment includes: a substrate; and a circuit pattern disposed on the substrate, wherein the circuit pattern includes a plurality of first circuit patterns, a plurality of second circuit patterns, and a plurality of third circuit patterns, wherein the third circuit pattern includes a third-first pad portion, a third-second pad portion, and a third wiring portion connecting the third-first pad portion and the third-second pad portion, a plurality of fourth wiring portions are disposed between a plurality of third wiring portions, a line width of the third wiring portion is greater than a line width of the fourth wiring portion, and a distance between the third wiring portion and the fourth wiring portion adjacent to the third wiring portion is greater than a distance between the fourth wiring portions.

The application discloses a novel flexible printed circuit board and camera module prepared based on weldable low-temperature silver paste, and belongs to the technical field of electronic materials and devices. The conductor pattern in the flexible printed circuit board comprises a main circuit pattern and an auxiliary function structure formed by weldable low-temperature cured silver paste. The curing temperature of the weldable low-temperature silver paste is 87-103 DEG C. The silver paste comprises conductive fillers, a polymer resin system, ester solvents, a curing agent, a silane coupling agent, polyamide wax thixotropic agents, polysiloxane defoaming agents, modified carbon nanotubes, modified antimony tin oxide powder, modified ceramic fillers and low-stress modifiers. The polymer resin system comprises hydrogenated bisphenol A type epoxy resin, diphenyl type epoxy resin and polyacrylate-CTBN copolymer. The conductive fillers comprise silver-coated copper flaky powder, nano silver wire and low-temperature alloy powder. Through the synergistic effect of components and the innovative process, the comprehensive improvement of mechanical properties, conductive properties, high-frequency characteristics and welding reliability is realized under the premise of ultralow-temperature curing.

The invention belongs to the technical field of graphene, and particularly relates to graphene leather capable of realizing temperature-sensitive color development and a preparation method of the graphene leather. As the graphene heating functional layer adopts the high-thixotropic silver paste, the printed circuit pattern is clear in edge, uniform in thickness and extremely high in consistency with the designed pattern; and a clear interface is formed between a silver paste circuit and leather fibers, and improper penetration is avoided. And the circuit resistance value consistency is excellent (the deviation is controlled within + / -5%), so that rapid, uniform and stable planar heating can be realized after the graphene heating layer is connected, and the local overheating hidden danger is perfectly eliminated. According to the present invention, the natural texture and the soft touch feeling of the leather are maintained while the efficient and safe heating performance with the visual color developing function is achieved.

The application discloses a method and device for feature extraction of integrated circuit layouts and a non-transitory computer readable storage medium thereof. A circuit pattern layout file to be implemented on a semiconductor wafer is obtained from a memory. Data preparation and preprocessing is performed on the circuit pattern layout file. A deep learning model is established and trained. Transfer learning and model fusion are performed on the deep learning model. The deep learning model is used to perform image segmentation and feature extraction on the circuit pattern layout file to extract a plurality of features. Density parameters and total perimeter parameters of the plurality of features are calculated.

This invention relates to a method for manufacturing a multilayer printed circuit board, comprising: a step of preparing a first circuit board; a step of preparing a metal laminate; a step of stacking the first circuit board on both sides of a carrier film to form a first multilayer laminate; a step of stacking the metal laminate on both sides of the first multilayer laminate to form a second multilayer laminate; a step of hot-pressing the second multilayer laminate; a step of forming a second circuit pattern on the metal foil of the hot-pressed second multilayer laminate to form a third multilayer laminate; and a step of separating the carrier film and the first circuit board from the third multilayer laminate to obtain two multilayer printed circuit boards having the first circuit board and the second circuit board stacked on them, respectively, and adjusting the MFR of the dried film to be greater than the MFR of the first thermoplastic resin layer.

A circuit board according to an embodiment includes: an insulating layer including first to third regions; an outer layer circuit pattern disposed on upper surfaces of the first to third regions of the insulating layer; and a solder resist including a first portion disposed in the first region of the insulating layer, a second portion disposed in the second region, and a third portion disposed in the third region, wherein the outer layer circuit pattern has a first height, the third portion of the solder resist is disposed on an upper surface of the outer layer circuit pattern to have a second height, the first region includes a first sub-region and a second sub-region, the first portion includes a first sub-portion disposed in the first sub-region and a second sub-portion disposed in the second sub-region, an upper surface of the first sub-portion is positioned higher than the upper surface of the outer layer circuit pattern and lower than an upper surface of the third portion, an upper surface of the second sub-portion is positioned lower than the upper surface of the outer layer circuit pattern, and a surface roughness of the third portion of the solder resist is different from a surface roughness of the first portion of the solder resist.

A flexible circuit board includes a substrate, a plurality of circuit patterns disposed on the substrate, and a protective layer disposed on the circuit patterns, wherein each of the plurality of circuit patterns has a thickness greater than 8 µm and less than or equal to 25 µm, and wherein a thickness deviation between the plurality of circuit patterns is 0.5 µm to 3 µm. When the flexible circuit board is connected with a display panel, the display panel can have high performance and high current can flow through the display panel. The circuit pattern having the features according to the present invention is prevented from being damaged by high current.

The invention relates to a sensor for determining two measured variables of a gas. The sensor has at least a first sensor element and a second sensor element and two control connections. The first sensing element and the second sensing element are connected in series. The sensor element is arranged between the actuation connections. The first sensing element is provided with a first electronic equivalent circuit diagram, and the first electronic equivalent circuit diagram comprises a parallel circuit composed of a first resistor and a first capacitor. The second sensing element is provided with a second electronic equivalent circuit diagram, and the second electronic equivalent circuit diagram comprises a second capacitor.

The invention is applicable to the technical field of electronic design automation, and provides a cross-design software netlist data co-processing method, which comprises the following steps: acquiring first netlist data; wherein the first netlist data is used for representing a logic connection relationship among a plurality of electrical components in the first schematic diagram, packaging library information corresponding to the electrical components and the like; wherein the first schematic diagram is a schematic diagram constructed based on first design software; performing data format conversion on the first netlist data to obtain second netlist data; importing the second netlist data into second design software; wherein the second design software is different from the first design software; and generating a circuit diagram corresponding to the printed circuit board based on the second netlist data and the second design software. According to the method, when cross-software circuit diagram design is carried out, an engineer does not need to consume extra time in format adaptation and data verification, so that the method focuses on core design links such as circuit diagram layout and wiring, the design period is shortened on the whole, and the working efficiency is improved.

The present disclosure relates to a method of debugging a printed circuit board having at least one boundary-scan compliant device, the method using an electronic processing unit and comprising the steps of: retrieving boundary-scan properties of the at least one boundary-scan compliant device, the boundary-scan compliant device comprising a list of boundary-scan compliant circuit terminals of the at least one boundary-scan compliant device; selecting and displaying a circuit diagram of at least a portion of the device mounted on the printed circuit board, the circuit diagram comprising at least one device of a plurality of devices mounted on the printed circuit board and at least one other device of the plurality of devices, the other device comprising circuit terminals that are interconnected with circuit terminals of the device for visualizing at least the device, the other device and the interconnections. The present disclosure also relates to a corresponding debugging apparatus and to a corresponding computer program product.

A circuit board according to an embodiment includes: a first circuit layer; a first insulating layer disposed on the first circuit layer; a second circuit layer disposed on the first insulating layer; and a second insulating layer disposed on the second circuit layer, wherein the first circuit layer includes a first circuit pattern disposed along a peripheral direction of an outer side surface of the first insulating layer at a position closest to the outer side surface of the first insulating layer, wherein the second circuit layer includes a second circuit pattern disposed along a peripheral direction of an outer side surface of the second insulating layer at a position closest to the outer side surface of the second insulating layer, and wherein a first separation distance in a horizontal direction from the outer side surface of the first insulating layer to the first circuit pattern is different from a second separation distance in the horizontal direction from the outer side surface of the second insulating layer to the second circuit pattern.

To provide a composite metal foil in which a second copper layer is laminated on a nickel layer and which can be suitably used for a printed wiring board because a circuit can be formed by selective etching, the contrast between different kinds of metals is clear and can be easily identified, and erroneous detection and detection omission of a circuit pattern in image inspection and displacement in the case of multilayering hardly occur.SOLUTION: A composite metal foil comprising at least one layer structure of a first copper layer / a nickel layer / a second copper layer, wherein an absolute value of a difference between a lightness L * Cu value of a surface of the second copper layer and a lightness L * Ni value of a surface of the nickel layer on which the second copper layer is laminated is 15 or more.SELECTED DRAWING: Figure 1

The invention discloses an IBC photovoltaic cell and a preparation method thereof, and relates to the technical field of cell preparation, the IBC photovoltaic cell comprises a silicon substrate, the back surface of the silicon substrate is provided with a plurality of back surface first doped regions, back surface second doped regions and isolation groove regions which are alternately arranged, the isolation groove regions are groove isolation G regions, and the groove isolation G regions are arranged on the back surface of the silicon substrate. The back metallization circuit pattern of the IBC photovoltaic cell adopts an 0BB connection circuit pattern without a main grid connection line. According to the invention, an 0BB electrocoppering line without a main grid connecting line is adopted, so that a large number of trench isolation G regions do not need to be arranged at the positions of the patterned main grids I and II, the processing flow is simplified, and a cylindrical contact channel is formed through processes such as laser film opening and acid cleaning. The aluminum-titanium alloy barrier layer, the copper seed layer, the copper conductive layer and the antioxidant tin layer are adopted to construct the metal electrode, so that the non-silicon cost of the IBC photovoltaic cell is further reduced, meanwhile, the contact resistance between aluminum and polycrystalline silicon is lower, and compared with a silver-coated copper wire screen printing process, the electrical property of the cell is optimized.

The invention discloses a circuit diagram rasterization processing method and device, equipment and a storage medium, and relates to the technical field of circuit image processing. The method comprises the following steps: determining at least one graph segmentation line according to a target vertex coordinate set of a line contour diagram in a target circuit diagram, and dividing the line contour diagram to obtain at least two trapezoidal contour diagrams; according to the vertex coordinate set of the trapezoidal contour map, judging the map type of the trapezoidal contour map to obtain a target contour map type including a right-angled trapezoidal contour map and a non-right-angled trapezoidal contour map; and according to the target contour diagram type, segmenting the trapezoidal contour diagram to obtain at least one rectangular contour diagram and at least one right triangle contour diagram, and performing rasterization processing to obtain a rasterized circuit diagram. According to the scheme, the trapezoidal profile diagram is divided into the rectangular profile diagram and the right triangle profile diagram according to the type of the target profile diagram, and rasterization is carried out, so that the rasterization efficiency of the trapezoidal profile diagram is improved.

Provided is a photosensitive conductive paste capable of forming a high-precision circuit pattern and having a small shrinkage amount during firing of the circuit pattern. The photosensitive conductive paste contains a conductive powder (A) and a photosensitive organic component (B), the median particle diameter r of the particle size distribution of the conductive powder (A) is 3.0 μm or more and 6.0 μm or less, and the content V1 of the conductive powder (A) in all solid components is 37 vol% or more and 55 vol% or less.

The application discloses a novel smart phone flexible printed circuit board and module prepared based on weldable silver paste, and belongs to the technical field of electronic materials and devices. The conductor pattern in the flexible printed circuit board comprises a main circuit pattern and an auxiliary function structure formed by weldable low-temperature silver paste. The solidification temperature of the weldable low-temperature silver paste is 90 DEG C to 110 DEG C. The weldable low-temperature silver paste comprises conductive fillers, a polymer resin system, ester solvents, a curing agent, a silane coupling agent, a polyamide wax thixotropic agent, a polysiloxane defoaming agent, modified carbon nanotubes, modified antimony tin oxide powder, modified ceramic fillers and nano yttrium oxide. The polymer resin system comprises cashew phenol-based epoxy resin, hydrogenated bisphenol A epoxy resin and polyacrylate-CTBN copolymer. The application provides a solution suitable for smart phone high-density interconnection, micro jumper, dynamic bending compensation and micro pad direct packaging, and solves the problems caused by high-temperature process damage to elements, welding pre-plating and high-density integration.

The invention relates to the technical field of additive manufacturing, in particular to an advanced packaging RDL additive manufacturing method based on electric field driving spray deposition, and adopts an electric field driving spray deposition micro-nano 3D printing technology. Successively printing a first dielectric layer and a first circuit pattern layer formed by printing conductive paste on the substrate according to a set printing mode and process parameters; the method comprises the following steps: firstly printing a first dielectric layer, then continuously printing a second dielectric layer, punching the second dielectric layer, filling holes with conductive slurry to realize inter-layer circuit interconnection, then printing a second circuit pattern formed by printing the conductive slurry, and repeating the steps of printing the dielectric layer and the circuit pattern and the steps of punching and filling holes so as to complete the preparation of the multilayer RDL; according to the method, integrated rapid manufacturing of the multi-layer rewiring structure is achieved through direct printing and interlayer interconnection of the dielectric layers and the high-precision wires, the problems that a traditional RDL technology is complex, long in period and poor in flexibility are solved, particularly, the method has unique advantages in the design verification stage, and rapid prototype verification of the RDL can be achieved.

The invention discloses an integrated circuit image processing method, electronic equipment and a storage medium, and the method comprises the steps: obtaining a graph data set of a graph layer from a graph data file of an integrated circuit, determining the total number of graphs according to the graph data set, dividing the graph data set into at least one graph data group corresponding to the graph layer, and converting each graphic data group into the first bitmap of the corresponding graphic layer, fusing all the first bitmaps corresponding to the same graphic layer to obtain the second bitmap, and converting the second bitmap into the pixel map of the corresponding graphic layer, so that the graphic data of the graphic layer can be processed on the memory level, and a new pixel map of the graphic layer can be quickly generated. In this way, it is not needed to traverse each data in all data sets for operation and draw each pixel point every time in the prior art, the operation time is shortened, and therefore large-batch graphic data of an integrated circuit can be loaded and displayed in time.

The invention discloses a netlist generation method and system based on circuit diagram recognition, and relates to the technical field of circuit diagram recognition, semantic segmentation of a circuit diagram is triggered according to contents of a plurality of feature categories and corresponding positions, a corresponding binary mask is output, a corresponding connection line pixel is marked in the traversing process of the binary mask, and a netlist is generated. The method comprises the following steps of: acquiring a connecting line pixel, and performing recursive search on a peripheral position along the connecting line pixel until a boundary of the connecting line pixel cluster is found so as to determine a complete connected region, thereby realizing image recognition of the circuit diagram, introducing semantic segmentation of the circuit diagram, improving the accuracy of a binary mask, further improving the accuracy of the connected region, and further improving the accuracy of the connected region. The connection relation in the netlist is determined according to each continuous wire and the element mask, the element list in the netlist is determined according to recognition of the binary mask, and the element list and the connection relation are summarized to generate the netlist in a standard format, so that the accuracy of the netlist is improved.

An integrated circuit structure is provided. The integrated circuit structure includes a substrate, a patterned ground shield structure, and a shielded circuit. The patterned ground shield structure is disposed above the substrate. The patterned ground shield structure includes a central portion and branches. The branches are connected to the central portion. The branches substantially extend radially from a central point of the central portion and surround the central portion. The shielded circuit including at least one conductive line is located directly above the patterned ground shield structure.

The invention discloses a circuit board, which is characterized by comprising a lead wire for mounting a patch fuse, which forms a circuit pattern and is broken in the middle; a patch fuse which is mounted to a broken portion of the patch fuse mounting lead wire and blocks a current flowing through the circuit pattern when an overcurrent occurs; the pattern fuse wire and the patch fuse mounting wire are arranged in parallel, and the middle of the pattern fuse wire and the patch fuse mounting wire are disconnected; and a pattern fuse which is formed at a broken portion of the pattern fuse wire and blocks a current flowing through the circuit pattern when an overcurrent occurs. Therefore, even if the patch fuse is damaged, the pattern fuse can properly cope with the blocking capacity.

Provided is a semiconductor device which improves adhesion between an insulating substrate and a sealing material and achieves a reduction in device size. This semiconductor device includes an insulating substrate, a semiconductor element, and a sealing material. The insulating substrate includes an insulating layer, a front surface circuit pattern provided on the front surface of the insulating layer, and a rear surface circuit pattern provided on the rear surface of the insulating layer. The semiconductor element is bonded to the front surface circuit pattern. The sealing material seals the semiconductor element and the insulating substrate. The sealing material covers the outer peripheral portion of the rear surface circuit pattern such that a portion of the rear surface circuit pattern is exposed from the lower surface of the sealing material.

A package substrate according to an embodiment includes a first substrate; and a first chip mounted on the first substrate; wherein the first substrate includes: a first insulating layer including a first region overlapping the first chip in a vertical direction and a second region other than the first region; and a circuit pattern disposed on the first region and the second region of the first insulating layer; wherein the circuit pattern includes: a pad portion including a first portion disposed on an upper surface of the second region of the first insulating layer, a second portion buried in the first region of the first insulating layer, and a third portion including at least a part buried in the first region of the first insulating layer and connecting between the first portion and the second portion; wherein at least a part of the first chip is disposed in the first region of the first insulating layer; wherein the first region of the first insulating layer surrounds a lower surface and a side surface of the first chip, and wherein the first region and the second region of the first insulating layer are a single insulating layer.

This invention belongs to the field of simulation calculation technology, specifically relating to a simulation calculation method for temperature rise of oil-immersed distribution transformers under photovoltaic harmonic current. The steps include: constructing a photovoltaic grid-connected current model to obtain current waveforms under different distortion rates, and performing frequency domain decomposition to obtain the harmonic current components; establishing a geometric model of the oil-immersed distribution transformer; setting the number of turns and electromagnetic field boundary conditions for the high-voltage and low-voltage windings; constructing a transformer circuit diagram and coupling it to the electromagnetic field of the geometric model; solving for winding losses and core losses of the high-voltage and low-voltage windings under different harmonic current components; meshing the thermal structure and setting boundary conditions for the temperature field; using winding losses and core losses as equivalent heat sources and employing a steady-state solver to obtain the temperature distribution results of the oil-immersed distribution transformer under different distortion rates. This invention can improve the accuracy of temperature rise calculation and also provide an optimization basis for transformer design.

A circuit board according to an embodiment includes a first insulating layer, a coating layer disposed on the first insulating layer, and a circuit pattern layer disposed on the coating layer, wherein the circuit pattern layer includes a first metal layer disposed on the coating layer, and a second metal layer disposed on the first metal layer, wherein the coating layer includes a first functional group bonded to the first insulating layer, and a second functional group bonded to the first metal layer.

Disclosed are processes and materials for adhesive circuit patterning which strengthen and protect printed circuit traces and adhesive bonded joints of surface mounted devices in flexible or stretchable electronics in a single process. A method for adhesive circuit pattering include deposing a circuit pattern directly on a single thermal adhesive film, placing one or more surface mounted devices on a cured deposed circuit of the deposed circuit pattern, curing the one or more surface mounted devices and the cured deposed circuit together to form an assembled deposed circuit, placing the assembled deposed circuit on a stretchable substrate, and melting the single thermal adhesive film directly onto the assembled deposed circuit and the stretchable substrate to reinforce joint bonds of the assembled deposed circuit and to attach the assembled deposed circuit to the stretchable substrate.