905 results about "Circuit graph" patented technology

An overall layout design unit (15) comprises: a neighboring block layout pattern design unit (31) that generates, for each circuit diagram group, one or more layout patterns, within the circuit diagram group, for a plurality of neighboring blocks included in the circuit diagram group; a circuit diagram group area pattern design unit (32) that generates one or more area patterns representing the areas for a plurality of circuit diagram groups on the board; and an overall layout pattern design unit (33) that generates, for each area pattern, one or more overall layout patterns in which one or more neighboring blocks included in a plurality of circuit diagram groups in the area pattern are laid out in a layout pattern in the areas for the circuit diagram groups.

The invention discloses a manufacturing process of a circuit board structure of aviation equipment, which comprises the following steps of: providing a carbon fiber reinforced ceramic substrate, after desizing process treatment, coating high-temperature ceramic slurry on the carbon fiber reinforced ceramic substrate, forming a high-temperature-resistant base material layer through vacuum drying, coating an electromagnetic shielding material on the surface of the base material layer, and forming the circuit board structure of the aviation equipment. Designing a circuit pattern, and transferring the circuit pattern to the electromagnetic shielding layer through a laser cutting or etching process to form a circuit layout; wiring the copper alloy film according to the circuit pattern, and combining the copper alloy film with the polymer composite material middle layer through a lamination process to form an electrical connection layer; coating the surface of the circuit board with a resin material, performing curing treatment, mounting a metal connecting piece in the edge area of the circuit board, performing connection in a crimping manner, then performing a 3D printing process, and printing connecting points on the surface of the circuit board; the circuit board provided by the invention has the advantages of high temperature resistance, electromagnetic interference resistance, support and excellent protection performance.

A semiconductor device includes a lower circuit pattern, a bit line shielding structure, a first insulating interlayer, a bit line structure, a first contact plug, a channel, and a capacitor. The lower circuit pattern is on the substrate. A bit line shielding structure is on the lower circuit pattern. A first insulating interlayer is in an opening extending through the bit line shielding structure. The bit line structure is on the bit line shielding structure and at least partially overlaps the bit line shielding structure in a vertical direction substantially perpendicular to the upper surface of the substrate. A first contact plug extends through the first insulating interlayer to contact the bit line structure and is electrically connected to the lower circuit pattern. A channel is on the bit line structure. A capacitor is on and electrically connected to the channel.

The invention provides a manufacturing method of a space converter of a probe card. The manufacturing method comprises the following steps: sequentially forming a titanium layer and a first copper layer on the upper surface of a ceramic substrate; forming a first circuit pattern on the upper surface of the first copper layer; forming a second copper layer on the first circuit pattern; removing the titanium layer and the first copper layer except the titanium layer below the second copper layer; sequentially forming a nickel layer and a first gold layer on the upper surface of the structure; forming a polyimide layer on the upper surface of the structure; removing the polyimide layer on the upper surface of the target position of the first gold layer to form a second circuit pattern; forming a first nickel-cobalt alloy layer on the second circuit pattern, and then forming a third circuit pattern; forming a second nickel-cobalt alloy layer on the third circuit pattern, and then forming a fourth circuit pattern; forming a second gold layer on the fourth circuit pattern; and removing the photoresist to obtain the space converter. According to the manufacturing method of the space converter of the probe card, the installation position of the probe can be accurately adjusted, and the alignment precision of the probe is improved.

The invention relates to the field of digital circuit experiment teaching, in particular to a digital circuit experiment platform and method applying a multi-modal large model and a medium, and the method comprises the steps: inputting experiment task description, analyzing and extracting structured semantic information, and forming task representation; retrieving a circuit function block from the electronic component knowledge base, constructing a context enhancement cue word, guiding a multi-modal large language model to generate a Verilog HDL code, and outputting the Verilog HDL code after grammar check and function verification; a Yosys tool is used for carrying out logic synthesis on the codes to generate a standard JSON netlist, and then the standard JSON netlist is converted into an SVG-format circuit diagram through a Netlistsvg tool; and an electronic component knowledge base updating mechanism is constructed to realize knowledge cyclic evolution and adaptive enhancement, so that the intelligent level and practical training efficiency of circuit experiment teaching are remarkably improved.

The invention discloses a manufacturing method of an insulating printed circuit board based on high voltage resistance. The manufacturing method comprises the following steps: S1, mixing ceramic powder and polyimide, and heating and curing to form a base material; s2, pollutants on the surface of the base material are removed through a plasma cleaning technology, and the binding force of the base material and a subsequent layer is improved; s3, transferring a circuit pattern to the surface of the base material on the base material through a laser direct writing technology; s4, performing deposition on the circuit pattern through a vacuum deposition technology to form a copper film layer; s5, performing mask manufacturing by using photoresist, and removing the copper film layer which is not covered by the mask through wet or dry etching to form a circuit; s6, a laser drilling technology is used for drilling micropores, and the inner walls of the micropores are metalized through a chemical copper plating technology; and S7, after circuit manufacturing is completed, ultraviolet light curing epoxy resin is used as an insulating coating. The circuit board material and the implementation method are innovated, so that the problems in the prior art are solved, and the voltage resistance, the insulating property and the reliability of the circuit board are improved.

The invention relates to the field of image defect detection, in particular to an SMT defect detection method and system based on image recognition, and the method comprises the steps: shooting a to-be-detected circuit board through an optical detection device to obtain an original circuit image, carrying out the illumination compensation of the original circuit image to obtain a target circuit image, carrying out the two-dimensional wavelet decomposition of the target circuit image, and carrying out the detection of the SMT defect. The method comprises the steps of obtaining a horizontal component floating-point diagram and a vertical component floating-point diagram, performing edge identification on a target circuit image according to the horizontal component floating-point diagram and the vertical component floating-point diagram to obtain an edge pixel point set, clustering the edge pixel point set by using the number of elements to obtain a plurality of element edge point sets, and constructing a plurality of surface-mounted component areas based on the plurality of component edge point sets, determining a defect component area group in the plurality of surface-mounted component areas, and transmitting the defect component area group to a display device. According to the invention, the accuracy of SMT mounting defect detection can be improved, and the defect response speed of a production line is improved.

The invention provides a circuit diagram solving method and device based on a multi-modal model and electronic equipment, and the method comprises the steps: inputting a to-be-solved circuit diagram into a pre-trained netlist recognition model, and outputting a netlist text; inputting the netlist text into a circuit simulator for circuit simulation to obtain a simulation result; obtaining a final answer based on the simulation result and the question text of the user; wherein the netlist identification model is a multi-modal model and is obtained by training based on a sample circuit diagram and a netlist label text, and due to the fact that the problem that an existing multi-modal large model cannot accurately understand circuit topology is effectively solved through the pre-trained netlist identification model; the problem that the mathematical reasoning calculation capability of an existing multi-mode large model is insufficient is solved through the circuit simulator, and therefore the method can analyze the circuit diagram more accurately.

The invention provides a circuit deposition method and device, and relates to the field of electronic circuit manufacturing, and the method comprises the following steps: preparing a deposition solution; deploying a dripping path of the deposition solution on a sample to be processed according to a preset circuit pattern; and dropwise adding the deposition solution on the sample along a dropwise adding path, and irradiating a dropwise adding region by using laser, so that an oxidation-reduction reaction occurs on the sample, thereby forming a line. The method is based on a laser-induced liquid phase deposition technology, a deposition solution containing metal ions is dropwise added to a sample to be processed according to a preset circuit pattern, laser is further used for irradiating a dropwise adding area, and a needed pattern circuit is formed along with movement of a laser irradiation position. The deposition device applying the method is simple in operation step and does not need post-treatment, and a simplified and environment-friendly solution is provided for the circuit manufacturing industry.

A smart IC substrate according to an embodiment includes: a substrate including one surface and the other surface; a circuit pattern and a connection circuit pattern disposed on the one surface; and a coil pattern disposed on the other surface, wherein a chip mounting region is formed on the other surface, the coil pattern is electrically connected to a first terminal and a second terminal, the substrate includes a first region disposed inside the coil pattern and a second region disposed outside the coil pattern, the first terminal is disposed in the first region, the second terminal is disposed in the second region, a first via is formed in the first region corresponding to the circuit pattern of the substrate, a second via is formed in the second region of the substrate, a third via is formed in the first region corresponding to the connection circuit pattern of the substrate, and a connection member is disposed inside the second via.

The embodiment of the invention discloses a cross-level gating conversion method and device, equipment and a storage medium, and the method comprises the steps: obtaining a target gating circuit diagram; identifying a connection relationship between devices in the target gating circuit diagram, and determining at least one clock path according to the connection relationship; wherein the clock path is used for representing a signal transmission path from the register to the top port; compiling a device in the clock path into a corresponding integrated unit so as to complete a conversion process of the target gating circuit diagram; wherein the integrated unit represents a device set composed of at least one register. According to the technical scheme, the clock paths in the circuit diagram can be automatically recognized, the devices in the clock paths are compiled into the corresponding integrated units, a large number of fan-out devices do not need to be processed in the conversion process, the logic copy amount is reduced, system resource consumption is reduced, and the device compiling efficiency is improved by conducting device compiling based on the clock paths. Original hierarchical structures between devices can be retained.

A printed circuit board according to an embodiment comprises: an insulating layer; a circuit pattern disposed on the upper surface of the insulating layer; a support layer which is disposed on the upper surface of the insulating layer to expose the upper surface of the circuit pattern and is in contact with the sides of the circuit pattern; and a protective layer disposed on the upper surfaces of the support layer and the circuit pattern, wherein the upper region of the insulating layer comprises a first region and a second region, and the protective layer comprises an open region exposing the upper surfaces of the support layer and the circuit pattern that are disposed in the first region, and the support layer comprises a first upper surface positioned at the highest level among the upper surfaces of the support layer and a second upper surface positioned at the lowest level among the upper surfaces of the support layer, the second upper surface being lower than the first upper surface, and the protective layer comprises a first portion which contacts the upper surface of the circuit pattern of the first region and a second portion which contacts the upper surface of the support layer of the first region, and the second portion of the protective layer contacts the second upper surface of the support layer and includes a first lower surface which is lower than the upper surface of the circuit pattern.

The invention provides a production process of a chip superfine circuit, relates to the field of intelligent chip production, and adopts an image processing and analysis technology based on deep learning to perform feature extraction and significant feature optimization of a circuit pattern microscopic image and a circuit pattern design image. And automatically generating a defect detection result based on comparison between a semantic interaction matching coefficient between the optimized microscopic image and the optimized design image feature and a preset threshold value. Therefore, tiny defects which are difficult to find by a traditional method can be identified, and the detection sensitivity and accuracy are improved. And meanwhile, the system can adapt to different types of defects and different batches of wafers, and the flexibility and the automation level of the detection system are improved.

The invention relates to the technical field of high-density circuit boards, and particularly discloses a high-density circuit board and method based on an electroplating solar etching process, and the method comprises the steps: obtaining a circuit pattern image collected by an industrial camera, extracting a circuit pattern design image from a database, and then carrying out the calculation of the circuit pattern design image; the method comprises the following steps: respectively carrying out feature extraction on a circuit pattern image and a circuit pattern design image by adopting an image analysis and processing technology based on deep learning, and carrying out significant interactive fusion to obtain circuit pattern detection-design significant sparse interactive fusion features; and based on the circuit pattern detection-design significant sparse interactive fusion features, automatically detecting whether the circuit pattern has defects or not. Therefore, through the automatic image processing technology, the defects on the circuit board can be identified and detected more intelligently, and the detection efficiency and accuracy can be improved.

The invention discloses a dry pattern transfer method for an AMB copper-clad ceramic substrate in the technical field of ceramic substrate sintering, and the method comprises the following steps: S1, manufacturing a positioning hole, and forming a process reference; s2, prefabricating a circuit pattern through a stamping process; s3, brazing material layers are printed on the two faces of the ceramic substrate; S4, the copper layer pattern and the ceramic substrate are assembled in an aligned mode; s5, carrying out high-temperature sintering on the copper layer and the ceramic substrate, and carrying out metallurgical bonding; and S6, the sintered substrate is subjected to cleaning, surface treatment and laser precision cutting. According to the method, laser positioning and micron-sized reaming are adopted, an accurate alignment reference is established, mechanical assembly errors are fundamentally eliminated, a copper circuit directly forms a preset pattern on a substrate through cooperation of a copper block pre-forming structure and an accurate brazing process, the lateral corrosion problem of a traditional etching process is avoided, and the production efficiency is improved. The size error of the product graph is reduced, and the product graph accuracy and the machine graph size consistency are improved.

The invention belongs to the field of electronic design automation (EDA), and particularly provides a logic comprehensive optimization operator acceleration method, which introduces a screening strategy of a sub-circuit diagram, and improves the optimization efficiency of an operator on the premise of ensuring the optimization quality of the operator. According to the method, the sub-circuit diagrams are classified by using the graph neural network, and the sub-diagrams suitable for operator execution are screened out, so that all the sub-diagrams are prevented from being traversed, and the operator execution speed is increased; in the sub-graph screening, a screening range is set according to the execution sequence of operators, a relatively large screening range is set for the operators executed firstly so as to obtain a better optimization effect, and a relatively small screening range is set for the operators executed later so as to obtain a higher execution speed; in conclusion, the characteristic that the logic comprehensive optimization operator is continuously executed in a sequence mode is utilized, and the operator optimization efficiency is improved on the premise that the operator optimization quality is guaranteed.

The invention discloses a power line troubleshooting practical training device which comprises an operation panel and a power supply module. The operation panel is used for arranging wires according to a preset circuit diagram and is detachably provided with a plurality of analog switches, a plurality of fault indicators, a display operation screen, a plurality of fault points, a plurality of data acquisition terminal units and a core control module; the power supply module is used for supplying power to the operation panel; the analog switch simulates switching on and switching off in a manual or automatic mode so as to achieve the effect of power supply switching. The fault point can simulate a fault condition; the fault indicator is connected with a specified fault point; the core control module is connected with the fault indicator and the data acquisition terminal unit, and is used for selecting the fault type and fault point setting of the current simulation line according to the signal of the display operation screen, and simulating the common fault type. According to the invention, a real-time simulation technology is adopted, so that trainees can carry out troubleshooting and processing in an approximately real environment, and thus the fault handling capability is improved.

The invention provides a method for stacking core particles on a wafer and a semiconductor device. The method comprises the following steps of: S1, arranging the wafer in a laminating device in a manner that one surface with a circuit pattern structure faces downwards; s2, absorbing the upper surface of a wafer from top to bottom by using a wafer absorbing device, and placing the wafer in the laminating device in a manner that one surface with a circuit pattern structure faces upwards; and S3, carrying out bonding by taking the direction from bottom to top as the bonding direction from the wafer to the wafer, and completing the stacking of the core particles on the wafer. According to the invention, particle pollution introduced by intermediate processes (such as cutting, picking, overturning and the like of a chip) in processing engineering is avoided, so that the technical problems of bonding strength reduction and bonding electrical failure are greatly avoided.

The invention discloses a novel automobile back view mirror flexible printed circuit board prepared based on weldable silver paste, and belongs to the technical field of electronic materials and devices, conductor patterns in the flexible printed circuit board comprise a main circuit pattern and an auxiliary function structure formed by weldable low-temperature curing silver paste; the curing temperature of the weldable low-temperature silver paste is 125-135 DEG C, and the weldable low-temperature silver paste comprises conductive filler, a polymer resin system, a high-boiling-point ester solvent, a curing agent, a silane coupling agent, a polyamide wax thixotropic agent, a polysiloxane defoaming agent, modified carbon nanotubes, modified aluminum oxide powder, modified barium sulfate and a low-stress modifier. The polymer resin system comprises novolac epoxy resin, biphenyl epoxy resin and a polyacrylate-CTBN copolymer; through the synergistic effect of all the components and an innovative process, comprehensive improvement of mechanical reliability, environmental durability, conductive stability and power load capacity is achieved, and the strict requirement for high reliability of the automobile rearview mirror in an extreme environment is perfectly met.

The invention discloses a novel notebook flexible printed circuit board prepared based on weldable low-temperature silver paste and a backlight module, and belongs to the technical field of electronic materials and devices. Conductor patterns of the flexible printed circuit board comprise a main circuit pattern formed by rolled copper; the auxiliary function structure is formed in a local area of the main circuit pattern by weldable low-temperature silver paste; the curing temperature of the weldable low-temperature silver paste is 130-145 DEG C, the weldable low-temperature silver paste comprises conductive filler, a polymer resin system, an ester solvent, a curing agent, a silane coupling agent, a polyamide wax thixotropic agent, a polysiloxane defoaming agent, modified carbon nanotubes and modified antimony tin oxide powder, and the conductive filler comprises flaky silver powder, spherical silver powder and low-temperature alloy powder. The low-temperature alloy powder is Sn42Bi58 low-temperature alloy powder of which D50 is 12 [mu] m-15 [mu] m; according to the invention, low-temperature curing, high flexibility, excellent conductivity and direct weldability are integrated, and a solution suitable for local repair of a flexible printed circuit board and direct mounting of a jumper and a Mini LED chip is provided.

A method and corresponding apparatus train a circuit topology generator. The method transforms a training circuit topology into a hierarchical graph in a high-dimensional data space. Nodes of the hierarchical graph correspond to selected subgraphs forming a subgraph basis. The selected subgraphs represent circuit elements of the topology. The method converts the hierarchical graph into a directed acyclic graph (DAG) to be processed by a circuit graph neural network (CktGNN) into a latent space. The latent space is a lower-dimensional data space relative to the high-dimensional data space. The method transforms the DAG into an estimated circuit topology via the circuit topology generator and trains the CktGNN and circuit topology generator based on differences between the training circuit topology and estimated circuit topology toward causing the circuit topology generator to converge on the training circuit topology. The trained circuit topology generator may be employed to generate novel circuit topologies, automatically.

The present invention discloses a method, system, device and medium for defect detection in the gold finger area of a circuit board, which relates to the field of electronic component production. After obtaining an image of the circuit to be measured, a target detection framework based on deep learning is used to locate the gold finger image area in the circuit to be measured. The image of the circuit to be measured is segmented according to the coordinates of the gold finger image area in the image of the circuit to be measured to obtain a gold finger area image. Then, the gold finger area image is analyzed to obtain the defect detection result of the printed circuit board. It can automatically detect the defects existing in the gold finger area of the printed circuit board by computer, avoiding the problems of unstable and inaccurate detection results obtained by manual visual inspection for gold finger areas with relatively similar features, and has strong practicability.

The invention discloses a multilayer printed circuit board wiring process, and relates to the technical field of electronic circuit board manufacturing, and the method comprises the steps: obtaining a wiring target and preset parameter conditions of a multilayer printed circuit board; calculating a target connection mode by adopting a circuit board wiring model based on the wiring target of the multi-layer printed circuit board and preset parameter conditions; coating photoresist on an inner-layer copper foil of the middle-layer substrate, transferring a circuit pattern to the copper foil through exposure and development processes according to a wiring target path, target layer selection, a target via hole position and a target element position, and drilling at a specified position by using a drilling machine; forming a conductive layer on the hole wall of the hole through an electroplating process; and repeating the manufacturing process of the inner layer of the middle-layer substrate on the outer-layer copper foil of the middle-layer substrate according to the wiring target path, the target layer selection, the target via hole position and the target element position to form an outer-layer circuit pattern. The efficiency of the wiring process of the printed circuit board is improved.

The invention relates to the field of artificial intelligence, natural language processing and electronic design automation, in particular to a circuit analysis generation and modification method based on form and logic separation, comprising the following steps: step 1, a complete circuit generation process; 2, separating and analyzing logic and form; step 3, intelligently modifying an operator; and step 4, labeling-generating-modifying a system: step 1, converting a natural language to a DSL code, then converting the DSL code into a logic diagram structure, and finally generating a morphological layout and a complete circuit diagram. According to the method, a complete process from a natural language to DSL, a logic diagram, morphological layout and a final circuit is achieved, the intelligent degree of circuit analysis is improved, through morphological and logic decoupling, the generalization ability of circuit analysis is improved, the complete automatic process from natural language description to final circuit generation is achieved, meanwhile, efficient circuit modification and optimization are supported, and the method is suitable for popularization and application. The method also provides a modification operator, supports accurate circuit adjustment, and improves the design efficiency.

The invention discloses a PCB processing technology for printing multi-layer stepped thick gold plating, and belongs to the field of multi-layer PCB processing. The PCB processing technology for printing multi-layer stepped thick gold plating comprises the following steps: designing a PCB, and carrying out hierarchical planning; overlapping and laminating the insulating material and the copper foil layer according to the design, and performing interlayer alignment by using an optical alignment system; laser drilling equipment is adopted to drill holes in the laminated plate for electrical connection and hole penetrating; a chemical nickel-copper plating process is used, and plating is carried out in the hole wall; forming a circuit pattern on the surface of the plating layer by using a photoetching technology; redundant materials are removed by using an etching technology; plating thick gold on the copper layer by using an electroplating technology; and measuring the thickness of the gold-plated layer, assembling the processed PCB, and carrying out electrical test. In the laminating process, the optical alignment system is used for carrying out interlayer alignment, so that the alignment precision is ensured, and the problems of signal transmission loss, short circuit or open circuit and the like are avoided.

According to the present invention, a semiconductor package is provided. A semiconductor package may include a package substrate, and a first semiconductor chip disposed on the package substrate, wherein the first semiconductor chip may include a semiconductor substrate including a first surface and a second surface opposite to the first surface, a circuit pattern region disposed on the first surface of the semiconductor substrate and including a plurality of circuit patterns, a signal wiring layer disposed on the circuit pattern region and electrically connected to the plurality of circuit patterns, and a power wiring layer disposed on the second surface of the semiconductor substrate and electrically connected to the plurality of circuit patterns through a plurality of through vias extending through the semiconductor substrate, and the package substrate may include a signal transmission pattern electrically connected to the signal wiring layer of the first semiconductor chip, and a power transmission pattern electrically connected to the power wiring layer of the first semiconductor chip.

The utility model relates to the technical field of circuit boards, and discloses a printed circuit board and an electronic device with the printed circuit board. The circuit board comprises a substrate and a circuit pattern printed on the substrate, and an acute included angle is formed between the whole circuit pattern and a glass fiber bundle of a dielectric layer of the substrate. According to the printed circuit board provided by the embodiment of the utility model, by rotating the circuit pattern, an acute included angle is formed between most of the wires in the circuit pattern and the glass fiber bundles of the dielectric layer, so that most of the wires in the circuit pattern can uniformly pass through the windows between the glass fiber bundles; and the delay inequality between the wires caused by the glass fiber effect is reduced, so that the delay inequality in the differential pair of the differential wire is reduced, and the performance of the circuit is improved.

The embodiment of the invention is suitable for the technical field of digital circuits, and provides a circuit analysis method and device, electronic equipment and a computer program product, and the method comprises the steps: obtaining description information of a to-be-analyzed circuit in different description modes; the description information in different description modes at least comprises a function abstract corresponding to a text description mode, a circuit diagram corresponding to a graphic description mode and a hardware description language corresponding to a programming language description mode; performing feature fusion on the single-mode features obtained based on the description information to generate fusion features of the circuit to be analyzed; inputting the fusion features into an analysis model, and generating an analysis result corresponding to the circuit to be analyzed; the analysis result corresponding to the analysis circuit comprises a correlation circuit corresponding to the to-be-analyzed circuit and / or a prediction index corresponding to the to-be-analyzed circuit. According to the method provided by the embodiment of the invention, the circuit to be analyzed can be analyzed according to the characteristics under various description information, so that the analysis accuracy of the circuit is improved.

The invention relates to the technical field of multi-order printed circuit boards, in particular to a multi-order printed circuit board, a processing method of the multi-order printed circuit board and a signal shielding groove, and the processing method of the multi-order printed circuit board comprises the following steps: carrying out pressing operation on the printed circuit board after circuit pattern arrangement is completed, sequentially pressing the insulating substrate and the copper foil on the printed circuit board; high-speed signal holes are formed in target positions of the insulating substrate and the copper foil; a signal shielding groove is formed in the outer side of the high-speed signal hole around the high-speed signal hole; performing chemical copper deposition and hole blocking and copper coating operation on the signal shielding groove; performing circuit pattern arrangement on the copper foil to obtain a printed circuit board on which circuit pattern arrangement is completed; and repeating the steps to obtain the multi-stage printed circuit board. According to the multi-stage printed circuit board, the processing method of the multi-stage printed circuit board and the signal shielding groove, the shielding capability of the high-speed signal hole can be improved, the transmission requirement of a higher-speed signal is ensured, and the loss caused by the influence of the surrounding environment in the signal transmission process is reduced.

A printed circuit board according to an embodiment includes a first insulating layer; a first circuit pattern disposed on a lower surface or inside the first insulating layer; a second circuit pattern disposed on an upper surface of the first insulating layer; a second insulating layer disposed on the upper surface of the first insulating layer and surrounding the second circuit pattern; and a protective layer disposed on an upper surface of the second insulating layer, wherein the second insulating layer has at least one recess formed on its upper surface, and wherein the protective layer is disposed in the recess formed on the upper surface of the second insulating layer.