3 results about "Binary frequency shift keying" patented technology

The invention relates to an open-loop modulation transmitter with a harmonic suppression switched capacitor power amplifier. The transmitter comprises a sixteen-phase delay locked loop, a binary frequency shift keying modulator and the harmonic suppression switched capacitor power amplifier. The sixteen-phase delay locked loop provides sixteen paths of clock signals with equal phase difference to the binary frequency shift keying modulator, and the sixteen paths of clock signals are used as input signals of the binary frequency shift keying modulator; the binary frequency shift keying modulator is connected with the harmonic suppression switched capacitor power amplifier and provides a modulation signal for the harmonic suppression switched capacitor power amplifier; and the harmonic suppression switched capacitor power amplifier is used for amplifying the modulation signal and suppressing a harmonic component so as to output the modulation signal after harmonic suppression. According to the invention, high data rate transmission can be supported, the higher harmonic suppression capability is provided, the design requirement of a matching network can be relaxed while the frequency spectrum purity is ensured, the chip area is reduced, and the system cost is reduced.

This invention belongs to the field of wireless communication technology and provides a low-jitter, low-reference-spurious orthogonal subsampling phase-locked loop (PLL). It includes a subsampling PLL and a frequency-locked loop. The subsampling PLL includes a functionally multiplexed QVCO, which is a Class F noise-cycled VCO. It comprises two identically structured Class F VCOs with I-core and Q-core noise cycles. The I-core and Q-core Class F VCOs achieve orthogonal outputs through cross-coupling of transistor gates. The sources of the oscillating transistors of both the I-core and Q-core Class F VCOs are connected in series with transistors and form a sixth-order resonant cavity, creating a noise-cycled path. The source output signal of the oscillating transistor is sent to a gate-isolated subsampling phase detector. The sampling switch of the gate-isolated subsampling phase detector is isolated from the outputs of the I-core and Q-core Class F VCOs by transistors to suppress binary frequency shift keying (BFS) effects. This invention features lower jitter, lower reference spurious emissions, lower power consumption, and a higher FoMJ value.

The invention relates to the technical field of radio frequency integrated circuits, and particularly discloses a sub-sampling phase discriminator for sampling ripple suppression. Two transmission gates which are always in a closed state are introduced on the basis of a traditional sub-sampling phase discriminator, the two transmission gates are respectively bridged between a VOP and a VSAMPN and between the VON and the VSAMPP, the ripple level of a sampling voltage is remarkably reduced through the structure, when the sub-sampling phase discriminator samples a forward input signal VOP, a forward sampling ripple is introduced, and the sampling voltage is reduced. A negative input signal VON transmits a negative sampling ripple through the closed transmission gate, and the introduced negative sampling ripple and the positive sampling ripple are superposed, so that the sampling ripple suppression effect is achieved, and the frequency of the modulation VCO is prevented from being frequently turned on and turned off by introducing the sub-sampling phase discriminator dummy, and the sampling ripple suppression effect is improved. Therefore, the influence of a binary frequency shift keying (BFSK) effect is obviously reduced.