This invention belongs to the field of
wireless communication technology and provides a low-
jitter, low-reference-spurious orthogonal subsampling phase-locked loop (PLL). It includes a subsampling PLL and a frequency-locked loop. The subsampling PLL includes a functionally multiplexed QVCO, which is a Class F
noise-cycled VCO. It comprises two identically structured Class F VCOs with I-core and Q-core
noise cycles. The I-core and Q-core Class F VCOs achieve orthogonal outputs through cross-
coupling of
transistor gates. The sources of the oscillating transistors of both the I-core and Q-core Class F VCOs are connected in series with transistors and form a sixth-order
resonant cavity, creating a
noise-cycled path. The source output
signal of the oscillating
transistor is sent to a gate-isolated subsampling
phase detector. The sampling switch of the gate-isolated subsampling
phase detector is isolated from the outputs of the I-core and Q-core Class F VCOs by transistors to suppress
binary frequency shift keying (BFS) effects. This invention features lower
jitter, lower reference spurious emissions, lower
power consumption, and a higher FoMJ value.