Low-jitter low-reference-spur quadrature sub-sampling phase-locked loop

Abstract

This invention belongs to the field of wireless communication technology and provides a low-jitter, low-reference-spurious orthogonal subsampling phase-locked loop (PLL). It includes a subsampling PLL and a frequency-locked loop. The subsampling PLL includes a functionally multiplexed QVCO, which is a Class F noise-cycled VCO. It comprises two identically structured Class F VCOs with I-core and Q-core noise cycles. The I-core and Q-core Class F VCOs achieve orthogonal outputs through cross-coupling of transistor gates. The sources of the oscillating transistors of both the I-core and Q-core Class F VCOs are connected in series with transistors and form a sixth-order resonant cavity, creating a noise-cycled path. The source output signal of the oscillating transistor is sent to a gate-isolated subsampling phase detector. The sampling switch of the gate-isolated subsampling phase detector is isolated from the outputs of the I-core and Q-core Class F VCOs by transistors to suppress binary frequency shift keying (BFS) effects. This invention features lower jitter, lower reference spurious emissions, lower power consumption, and a higher FoMJ value.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication technology and provides a low-jitter, low-reference-spurious-orthogonal subsampling phase-locked loop. Background Technology

[0002] The ever-increasing demand for high-data-rate wireless and wired transceivers is driving the development of quadrature local oscillator clocks. These clocks effectively reduce the carrier frequency of subharmonic receivers and support circularly polarized radiation. Furthermore, quadrature clocks simplify data serialization design in high-speed communication systems while reducing the rate requirements of critical sampling modules in clock data recovery circuits. These communication systems typically require quadrature clocks to exhibit stringent low jitter and low reference spurious performance.

[0003] The main technologies for generating quadrature clocks currently include frequency dividers, multiphase filters, and injection-locked ring oscillators.

[0004] However, the frequency divider scheme relies on the phase-locked loop (PLL) to operate at twice the frequency, which brings additional circuit power consumption; multi-phase filters are more sensitive to device mismatch due to their narrow-band characteristics and are prone to introducing large quadrature phase errors; although injection-locked ring oscillators can suppress the phase noise of the ring oscillator by taking advantage of the excellent jitter filtering characteristics of injection-locked technology, they still require an additional frequency tracking loop to calibrate the quadrature phase error.

[0005] Quadrature PLLs are an attractive approach for generating quadrature clocks. Their root-mean-square (RMS) jitter is primarily determined by in-band noise and the out-of-band phase noise of the quadrature voltage-controlled oscillator (QVCO). Increasing the phase detector gain helps suppress in-band charge pump noise. Therefore, by increasing the phase detector gain and reducing the phase noise of the QVCO, the RMS jitter of the quadrature PLL can be effectively reduced. However, traditional charge pump PLLs have limited in-band noise suppression capabilities due to their low phase detector gain. Furthermore, the current mismatch of the charge pump periodically modulates the output frequency of the QVCO, resulting in significant reference spurious emissions.

[0006] As an alternative, orthogonal subsampling PLLs achieve higher phase detection gain by directly sampling the QVCO output using a reference signal (REF), thus significantly suppressing charge pump noise and making the in-band noise primarily determined by the reference signal. This characteristic allows orthogonal subsampling PLLs to achieve a better balance between jitter and power consumption, resulting in a superior jitter figure-of-merit (FoMJ). However, this architecture is often affected by effects such as binary frequency shift keying (BFSK), clock feedthrough, charge injection, and charge sharing, leading to relatively high reference spurious emissions. Furthermore, to achieve minimal jitter, orthogonal subsampling PLLs place extremely high demands on the phase noise of the QVCO.

[0007] In recent years, the academic community has proposed a variety of improvement schemes to address the problem of poor reference spurious performance of subsampled PLLs.

[0008] Xiang Gao et al., through in-depth analysis of the generation mechanism of reference spurious signals, proposed adding a virtual sampling capacitor to maintain a constant load on the voltage-controlled oscillator (VCO), thereby suppressing reference spurious signals caused by the BFSK effect. However, the process mismatch between the virtual capacitor and the sampling capacitor may affect the reference spurious signal suppression effect. Using a delay-locked loop (PLL) to align the two sides of the reference signal with the DC operating point of the VCO can alleviate reference spurious signals caused by charge injection and charge sharing, but it increases chip area and power consumption. Zunsong Yang et al. further proposed a gate-isolated sampling technique to enhance the isolation between the VCO and the subsampling phase detector. However, low in-band noise requires the phase detector to use a larger transistor, and its gate capacitance variation still modulates the VCO load, exacerbating the effects of clock feedthrough and charge injection. To reduce the impact of BFSK and charge injection effects, Haoran Li et al. proposed a functionally multiplexed VCO, merging the isolation buffer with the VCO to reduce noise and capacitive load. However, the load resistance in this structure causes voltage drop and increases power consumption. Hanzhang Cao et al. introduced magnetic isolation technology to suppress reference spurious signals, but this requires an additional high-frequency current-mode divider, which leads to power consumption overhead.

[0009] To reduce QVCO phase noise, traditional solutions typically employ two LC voltage-controlled oscillators and achieve quadrature outputs through active transistor cross-coupling. However, the active-coupled transistors introduce additional noise and power consumption. To eliminate these effects, Tianzuo Xi et al. proposed using transformer coupling to generate quadrature signals, but this design involves a trade-off between phase noise and quadrature phase accuracy.

[0010] Ya Zhao et al. further proposed a three-coil transformer-coupled quadrature voltage-controlled oscillator. By optimizing the transformer resonant cavity parameters, the above trade-off can be alleviated to some extent. However, the large source degradation inductance still leads to an increase in power consumption.

[0011] In summary, existing orthogonal subsampling PLLs still have significant shortcomings in jitter reduction and reference spurious suppression, and their QVCOs are unable to further reduce phase noise without increasing power consumption. Summary of the Invention

[0012] To address the aforementioned technical problems, this invention provides a low-jitter, low-reference-spurious orthogonal subsampling phase-locked loop (PLL) with lower jitter, lower reference spurious emissions, lower power consumption, and a higher quality factor (FoMJ) value.

[0013] The technical solution of this invention includes a subsampling phase-locked loop and a frequency-locked loop. The subsampling phase-locked loop includes a closed-loop reference clock buffer, a gate-isolated subsampling phase detector, a main charge pump array, a low-pass filter, and a functionally multiplexed QVCO. The frequency-locked loop includes a closed-loop differential-to-single-ended module, a frequency-to-phase detector with dead time, an auxiliary charge pump array, and a multi-mode divider. The functionally multiplexed QVCO is a noise-cycled Class F structure, including two identical noise-cycled I-core Class F VCOs and Q-core Class F VCOs. The I-core Class F VCO and Q-core Class F VCO achieve quadrature output through cross-coupling of transistor gates. The sources of the oscillating transistors of the I-core Class F VCO and Q-core Class F VCO are connected in series with transistors and a sixth-order resonant cavity is set to form a noise-cycled path. The output signal from the source of the oscillating transistor is sent to the gate-isolated subsampling phase detector. The sampling switch of the gate-isolated subsampling phase detector is isolated from the outputs of the I-core Class F VCO and Q-core Class F VCO by transistors to suppress binary frequency shift keying effects.

[0014] Furthermore, the structures of both I-core F-type VCOs and Q-core F-type VCOs include: The source pole and The source poles are connected. The drain is grounded. Gate capacitor and inductor The left end, Gate capacitor and inductor The right end, The drain is grounded. The source of M2 is connected to the source of M2. Gate capacitor and inductor The right end, Gate capacitor and inductor The left end, Drain and capacitor and inductor The left end is connected. Drain and capacitor and inductor The right end is connected to the inductor. center tap ,inductance center tap ,inductance center tap ,inductance and inductor Through coupling coefficient Coupling, inductor and inductor Through coupling coefficient Coupling, inductor and inductor Through coupling coefficient To couple.

[0015] Furthermore, the connection relationship between the I-core F-type VCO and the Q-core F-type VCO is as follows: the capacitance of the I-core F-type VCO... The lower end is connected to the Q core F-type VCO. Gate connection, capacitor of I-core F-type VCO The upper part is connected to the Q core F-type VCO. Gate connection, capacitance of Q-core F-type VCO The upper end is connected to the I-core F-type VCO. Gate connection, capacitance of Q-core F-type VCO The lower end is connected to the I-core F-type VCO. Gate connection.

[0016] Furthermore, the structure of the gate-isolated subsampling phase detector includes a first structure and a second structure arranged symmetrically. The first structure includes: Drain and source, capacitor The upper end connection, The source pole and drain, capacitor The upper end and connect, gate connection , gate connection ,capacitance The lower end is grounded, capacitor The lower end is grounded. and The public node is , Drain and Drain, The source connection, The source pole and Drain, The source pole, Drain and capacitor The upper end connection, gate connection , Drain and Drain, The drain connection, gate connection , gate connection , The source is grounded. source terminal , gate and The gates of the functionally multiplexed QVCO are all connected to the Node connections; the second structure has the same connection relationship as the first structure, and the second structure is connected to the functionally reused QVCO. Node connections.

[0017] Furthermore, the gate-isolated subsampling phase detector also includes two virtual sampling branches, which are distributed and connected to the first and second structures in the same way. The structure of the virtual sampling branches is as follows: The source pole and Drain and Drain connection, Drain and The source pole, The source pole, drain and capacitor The upper end connection, The gate is connected to the clock signal. , gate connection , drain connection The source pole, gate connection , source terminal The drain electrode, gate connection ,capacitance The lower end is grounded.

[0018] Furthermore, the main charge pump array includes multiple sets of main charge pumps connected in parallel, and the structure of the main charge pump includes: a power supply. Connecting resistors The upper part The source pole, The source and The source, resistor The lower end connects The drain and gate, The source is grounded. gate and gate connection, The source is grounded. Drain and The source connection, gate and The gate and node EN are connected. Drain and Gate and drain, gate, The drain connection, Drain and The drain and node ICP connection, The gate is connected to node VP. The gate is connected to node VN. The source pole and The source poles are all with The drain connection; the nodes VP of multiple main charge pumps are interconnected, the nodes VN are interconnected, and the node I... CP They are interconnected, but there are no connections between nodes EN.

[0019] Furthermore, there are 4 to 6 main charge pumps.

[0020] Furthermore, the auxiliary charge pump array includes multiple sets of auxiliary charge pumps connected in parallel, and the structure of the auxiliary charge pumps includes: a power supply. With resistance The upper part The source pole, The source pole, The source connection, resistor The lower end and drain and gate, gate, Drain and gate connection, The source pole, The source pole, The source and The sources are all grounded. Drain and drain and gate, Drain, gate connection, gate and The gates of all are connected to node EN. Drain and Drain, Drain, The source pole, The source connection, gate, gate, gate, The gates are all connected to the node connect, Drain and The source pole, The source pole, Drain, The drain connection, gate, gate, gate, The gates are all connected to the node connect, Drain and The source pole, The source of the extreme, The drain connection, Drain and The source pole, The source pole, Drain connection; node of multiple auxiliary charge pumps They are interconnected, nodes They are interconnected, node I CP1 They are interconnected, but there are no connections between nodes EN.

[0021] Furthermore, there are 2 to 4 auxiliary charge pumps.

[0022] The technical solution provided by this invention has the following advantages compared with the prior art: The subsampling phase-locked loop and the frequency-locked loop work together. The output signal of the reference clock buffer in the subsampling phase-locked loop is used to sample the output of the gate-isolated subsampling phase detector multiplexed QVCO. The transistor isolation design between the sampling switch and the QVCO output suppresses the binary frequency shift keying effect. The phase detection result is fed back to adjust the multiplexed QVCO by the main charge pump array and low-pass filter. The frequency-locked loop processes the QVCO signal through a differential to single-ended module. The frequency is calibrated by a phase detector with dead time, an auxiliary charge pump array, and a multi-mode divider. The I core and Q core of the multiplexed QVCO achieve quadrature output through gate cross-coupling. The series transistor at the source of its oscillating transistor and the sixth-order resonant cavity form a noise loop path to optimize oscillation characteristics. The dual loops work together to achieve precise phase locking. Compared with existing technologies, the functional multiplexing QVCO of this invention, with its noise-cycled Class F structure and sixth-order resonant cavity, effectively suppresses the noise of the start-up transistor and reduces phase noise without increasing additional power consumption. The gate isolation design significantly weakens the binary frequency shift keying effect and reduces reference spurious emissions. The gate cross-coupling of the I-core and Q-core ensures quadrature output accuracy, and the closed-loop architecture of the subsampling phase-locked loop and frequency-locked loop improves locking stability. Overall, through structural optimization, it achieves performance advantages of low jitter, low reference spurious emissions, and low power consumption, meeting the stringent requirements of wireless communication systems for quadrature clocks without relying on additional auxiliary modules.

[0023] Other advantages, objectives and features of the present invention will become apparent in part from the following description, and in part from those skilled in the art through study and practice of the invention. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a block diagram of an orthogonal subsampling PLL system according to an embodiment of the present invention.

[0026] Figure 2 This is a model of a Class F voltage-controlled oscillator and its equivalent noise level in the prior art.

[0027] Figure 3 (a) is a schematic diagram of the structure of a noise-cycled Class F voltage-controlled oscillator according to an embodiment of the present invention. Figure 3 (b) is a comparison of the thermal noise of the noise-cycled Class F voltage-controlled oscillator with existing technology.

[0028] Figure 4This is a schematic diagram of the QVCO (QVCO) functional reuse mechanism in an embodiment of the present invention.

[0029] Figure 5 This is a structural diagram of a gate-isolated subsampling phase detector according to an embodiment of the present invention.

[0030] Figure 6 This is a simplified model for stray analysis in the embodiments of the present invention.

[0031] Figure 7 This is a schematic diagram of the main charge pump array according to an embodiment of the present invention.

[0032] Figure 8 This is a schematic diagram of the auxiliary charge pump array according to an embodiment of the present invention.

[0033] Figure 9 This is a schematic diagram of a multimode frequency divider according to an embodiment of the present invention.

[0034] Figure 10 The output phase noise curve of the orthogonal subsampling PLL in this embodiment of the invention is shown.

[0035] Figure 11 This is the spectrum of the output signal of the orthogonal subsampling PLL in an embodiment of the present invention.

[0036] Figure 12 This is a power consumption decomposition of the orthogonal subsampling PLL in an embodiment of the present invention.

[0037] Figure 13 This is a curve showing the change of the phase-locked loop control voltage over time in an embodiment of the present invention. Detailed Implementation

[0038] The following detailed description of a specific embodiment of the present invention is provided in conjunction with the accompanying drawings. However, it should be understood that the scope of protection of the present invention is not limited to the specific embodiment.

[0039] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the technical solution of this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0040] In the description of the embodiments of the present invention, unless otherwise stated, "a plurality of" means two or more.

[0041] In the description of the embodiments of the present invention, VCO is a voltage-controlled oscillator.

[0042] In the description of the embodiments of the present invention, for ease of description, the description of transistors is omitted; the same applies to the other inductors, capacitors, and resistors, such as transistors. Write it directly .

[0043] like Figure 1 , Figure 3 (a) Figure 3 (b) Figure 4 As shown, this invention provides a low-jitter, low-reference-spurious-orthogonal subsampling phase-locked loop (PLL), comprising a subsampling PLL and a frequency-locked loop. The subsampling PLL includes a closed-loop reference clock buffer, a gate-isolated subsampling phase detector, a main charge pump array, a low-pass filter, and a functionally multiplexed QVCO. The frequency-locked loop includes a closed-loop differential-to-single-ended module, a frequency and phase detector with dead time, an auxiliary charge pump array, and a multi-mode divider. The functionally multiplexed QVCO is a Class F noise cycling structure, comprising two identical I-cores with the same noise cycling characteristics. The Class-A VCO and Q-core Class-F VCO, as well as the Class-A F VCO and Q-core Class-F VCO, achieve quadrature output through cross-coupling of transistor gates. The sources of the oscillating transistors of the Class-A F VCO and Q-core Class-F VCO are connected in series with transistors and a sixth-order resonant cavity is set to form a noise loop path. The output signal from the source of the oscillating transistor is sent to the gate-isolated subsampling phase detector. The sampling switch of the gate-isolated subsampling phase detector is isolated from the output of the Class-A F VCO and Q-core Class-F VCO by transistors to suppress binary frequency shift keying effect.

[0044] Specific working principle: In the initial stage of the orthogonal subsampling PLL operation, the switching control word of the functional multiplexed QVCO is adjusted so that the functional multiplexed QVCO operates in the frequency band near 10.5GHz. Next, VCOP and VCON are converted into a single signal through a differential-to-single-ended module, and then divided by a multi-mode divider to output the DIV signal. The divided signal DIV and the REF signal of the reference clock buffer are compared by a frequency and phase detector with dead time, outputting VUP and VDN signals to adjust the output current ICP1 of the auxiliary charge pump array. This, in turn, changes the control voltage VCTRL by charging and discharging the low-pass filter, adjusting the oscillation frequency of the functional multiplexed QVCO to get closer to 10.5GHz. At this time, the frequency locking loop will enter the dead time, and the output current I of the auxiliary charge pump array will... CP1 =0. Therefore, the frequency-locked loop does not contribute phase noise to the output of the final quadrature subsampling PLL. During this process, the gate-isolated subsampling phase detector samples the differential output signals VCON and VCOP of the QVCO using the output signals CLK1, CLK1N, CLK2, and CLK2N of the reference clock buffer. The output VCON and VCOP of the gate-isolated subsampling phase detector are equal to or less than 0 if and only if the sampling occurs at the DC operating points of VCON and VCOP. P =VN The output current I of the main charge pump array CP =0, the phase-locked loop completes the final phase locking. Otherwise, I CP The charging and discharging low-pass filter fine-tuning function reuses the output frequency of the QVCO until the quadrature subsampling PLL completes the final phase locking.

[0045] The jitter and quadrature phase accuracy of an orthogonal subsampling PLL are determined by the phase noise and phase accuracy of a functionally multiplexed QVCO. A QVCO is typically composed of two differential VCOs coupled together. Reducing the phase noise of a single-core VCO is key to achieving a low-noise QVCO. For example... Figure 2 As shown, based on the dual-port configuration of the Class F VCO and its equivalent phase noise model, and based on Hajimiri's linear time-varying phase noise model, the effective noise contribution of this VCO is:

[0046] in, It is a single-ended impulse sensitivity function. and respectively oscillation , and resonant cavity ( , , , The single-ended effective current noise power spectral density of the resonant cavity (composed of the VCO). The resonant cavity voltage gain AV of a Class F VCO helps to reduce... Furthermore, the third harmonic shaping technique reduces The function value is reduced, thereby reducing phase noise.

[0047] In the embodiments provided by this invention, the structures of both the I-core F-type VCO and the Q-core F-type VCO include: The source pole and The source poles are connected. The drain is grounded. Gate capacitor and inductor The left end, Gate capacitor and inductor The right end, The drain is grounded. The source of M2 is connected to the source of M2. Gate capacitor and inductor The right end, Gate capacitor and inductor The left end, Drain and capacitor and inductor The left end is connected. Drain and capacitor and inductor The right end is connected to the inductor. center tap ,inductance center tap ,inductance center tap ,inductance and inductor Through coupling coefficient Coupling, inductor and inductor Through coupling coefficient Coupling, inductor and inductor Through coupling coefficient To couple.

[0048] In the embodiments provided by this invention, the connection relationship between the I-core F-type VCO and the Q-core F-type VCO is as follows: the capacitance of the I-core F-type VCO... The lower end is connected to the Q core F-type VCO. Gate connection, capacitor of I-core F-type VCO The upper part is connected to the Q core F-type VCO. Gate connection, capacitance of Q-core F-type VCO The upper end is connected to the I-core F-type VCO. Gate connection, capacitance of Q-core F-type VCO The lower end is connected to the I-core F-type VCO. Gate connection.

[0049] To further reduce oscillation and To reduce thermal noise, this invention connects the source terminals of M1 and M2 in series respectively. and and using a sixth-order resonant cavity ( , , , , , The resonant cavity (composed of a resonant cavity) provides feedback to satisfy the resonance condition and enable noise cycling, such as... Figure 3 As shown in (a). The voltage gain provided by this invention enables the oscillating transistor ( and The equivalent transconductance of ) becomes:

[0050] in, for and transconductance, for and Transconductance. Due to and Due to source degradation, only a portion of the transistor's noise current reaches the resonant cavity and contributes to phase noise; the remainder is circulated to the ground plane. The equivalent noise current of the oscillating transistor can be derived as follows:

[0051] In the formula, K is the Boltzmann constant, taken as 1.380649×10−23 J / K, and T is the absolute temperature, usually taken as 300K at room temperature.

[0052] Assuming γn (channel noise figure of NMOS transistor) = γp (channel noise figure of PMOS transistor) = γ (defined transistor channel noise figure), and the transistor operates in the saturation region to neglect conductance Gds9 (drain and source conductance). Compared to a Class F VCO, the noise current of a noise-cycled Class F VCO will be reduced by a factor of (1 + AV / AV1), as shown in the appendix. Figure 3 As shown in (b).

[0053] Next, in order to obtain low-phase-noise quadrature-phase output, this invention proposes using two noisy cyclic Class F VCOs (I-core and Q-core), through the I-core... and and Q core and The gate-end cross-coupling is implemented, such as Figure 4 As shown, this functionally multiplexed QVCO has the advantages of in-phase resonant cavity voltage and current, avoiding the problem of resonant cavity Q-value deterioration in traditional QVCO.

[0054] In the embodiments provided by the present invention, such as Figure 5 As shown, the structure of the gate-isolated subsampling phase detector includes a first structure and a second structure arranged symmetrically. The first structure includes: Drain and source, capacitor The upper end connection, The source pole and drain, capacitor The upper end and connect, gate connection , gate connection ,capacitance The lower end is grounded, capacitor The lower end is grounded. and The public node is , Drain and Drain, The source connection, The source pole and Drain, The source pole, Drain and capacitor The upper end connection, gate connection , Drain and Drain, The drain connection, gate connection , gate connection , The source is grounded. source terminal , gate and The gates of the functionally multiplexed QVCO are all connected to the Node connections; the second structure has the same connection relationship as the first structure, and the second structure is connected to the functionally reused QVCO. Node connections.

[0055] It should be noted that, for ease of understanding, only the first structure is described. The transistors, capacitors and nodes in the second structure are connected in the same way as in the first structure, but the serial numbers are changed.

[0056] In the embodiments provided by the present invention, the gate-isolated subsampling phase detector further includes two virtual sampling branches. The two virtual sampling branches are distributed and connected to the first structure and the second structure in the same way. The structure of the virtual sampling branches is as follows: The source pole and Drain and Drain connection, Drain and The source pole, The source pole, drain and capacitor The upper end connection, The gate is connected to the clock signal. , gate connection , drain connection The source pole, gate connection , source terminal The drain electrode, gate connection ,capacitance The lower end is grounded.

[0057] The gate-isolated subsampling phase detector used in this invention achieves this by switching the sampling switch (i.e. Figure 5 Left side of the middle and A set of sampling switches, the one on the right and A gate-isolated transistor (i.e., a sampling switch) is used between the sampling switch and the VCO output. , , , Separating the two sides can significantly reduce the influence of the BFSK effect, thereby reducing the reference spurious signal of the output signal. The schematic diagram is attached. Figure 5 As shown, this subsampling phase detector exhibits a symmetrical structure, indicating subsampling of the differential signal output by the VCO. Simultaneously, this subsampling phase detector includes a virtual sampling branch, ensuring that the load of the functionally multiplexed QVCO remains constant during both the sampling and holding phases of the quadrature subsampling PLL, further reducing the degradation of reference spurious signals caused by the BFSK effect.

[0058] Furthermore, in this gate-isolated subsampling phase detector, at the instant the switching transistor is turned off and closed, the sampling voltage and holding voltage will fluctuate due to switching effects such as charge feedthrough and charge sharing. Therefore, all the switching transistors in this invention are transmission gate switches composed of NMOS and PMOS, so that the holes released by the PMOS transistor and the electrons released by the NMOS transistor when the switching effect occurs are neutralized, thereby reducing the charge feedthrough and charge sharing effects.

[0059] like Figure 6 As shown, the isolated sampling technique uses a gate-isolated subsampling phase detector at source S1 of the functionally multiplexed QVCO oscillators M1 and M3 to sample and hold the output signal, further increasing the isolation of the sampling capacitor C4 and the QVCO transformer resonant cavity, thereby significantly reducing reference spurious signals caused by the BFSK effect. Furthermore, since no buffer is used to isolate the QVCO and the subsampling phase detector, the power consumption of the quadrature subsampling PLL is reduced. Because S1 is a low-impedance path, some of the charge from Q1 and Q2 reaches S1 through the parasitic capacitances of isolation M15 and M25, and flows to ground through M7, further reducing the effects of charge injection and charge sharing, thereby further reducing reference spurious signals.

[0060] In the embodiments provided by the present invention, such as Figure 7 As shown, the main charge pump array includes multiple sets of main charge pumps connected in parallel. The structure of the main charge pump includes: a power supply. Connecting resistors The upper part The source pole, The source and The source, resistor The lower end connects The drain and gate, The source is grounded. gate and gate connection, The source is grounded. Drain and The source connection, gate and The gate and node EN are connected. Drain and Gate and drain, gate, The drain connection, Drain and The drain and node ICP connection, The gate is connected to node VP. The gate is connected to node VN. The source pole and The source poles are all with The drain connection is as follows: nodes VP of multiple main charge pumps are interconnected, nodes VN are interconnected, nodes ICP are interconnected, and nodes EN are not interconnected.

[0061] In the embodiments provided by the present invention, there are 4 to 6 main charge pumps, preferably 5.

[0062] When current mismatch occurs in the charge pump, the gate-isolated subsampling phase detector will deviate the sampling point from the DC operating points of the QVCO output VCON and VCOP to reduce the charge pump mismatch current. To achieve dynamic adjustment of the loop bandwidth, in the charge pump... and Add a switching transistor to the gate terminal Additionally, a cascaded switch M41 is connected at the tail of the current source. The enable control signals EN1 to EN5 (taking 5 main charge pumps as an example) control the number of charge pumps connected to the subsampling phase-locked loop to control the magnitude of the output current ICP.

[0063] In the embodiments provided by the present invention, such as Figure 8 As shown, the auxiliary charge pump array includes multiple sets of auxiliary charge pumps connected in parallel. The structure of the auxiliary charge pump includes: a power supply. With resistance The upper part The source pole, The source pole, The source connection, resistor The lower end and drain and gate, gate, Drain and gate connection, The source pole, The source pole, The source and The sources are all grounded. Drain and drain and gate, Drain, gate connection, gate and The gates of all are connected to node EN. Drain and Drain, Drain, The source pole, The source connection, gate, gate, gate, The gates are all connected to the node connect, Drain and The source pole, The source pole, Drain, The drain connection, gate, gate, gate, The gates are all connected to the node connect, Drain and The source pole, The source of the extreme, The drain connection, Drain and The source pole, The source pole, Drain connection; node of multiple auxiliary charge pumps They are interconnected, nodes Nodes are interconnected, nodes ICP1 are interconnected, and nodes EN are not interconnected.

[0064] In the embodiments provided by the present invention, there are 2 to 4 auxiliary charge pumps, preferably 3.

[0065] The charge pump's switches M51 to M58 are designed with a symmetrical structure to ensure the current source transistors above and below the switching transistors are connected. and The drain voltage is approximately constant to prevent periodic fluctuations in the VCTRL voltage. Simultaneously, a transmission gate switch is used to reduce the on-resistance of the switching transistor and facilitate the transmission of high and low levels. Furthermore, pull-up resistors M61 and M47 are connected to the gate terminals of the upper and lower current source transistors, respectively. When external digital control signals EN6 to EN8 (taking three auxiliary charge pumps as an example) turn on M61 and M47, and The gate voltage will be pulled up to the power supply VDDH and pulled down to the ground plane VSS, respectively, causing the current source transistor to... and When turned off, the charge pump will not output current, thus enabling dynamic adjustment of the final output current ICP1 and regulating the loop bandwidth of the frequency-locked loop.

[0066] As attached Figure 9 As shown, in order to reduce the operating frequency of the multi-mode frequency divider, the frequency of the output OUT signal of the QVCO is first divided by a frequency divider composed of dynamic D flip-flops. Then, in order to achieve frequency division in the range of 16 to 31, four cascaded 2 / 3 frequency dividers are used. In order to realize the function of the frequency division control words Ndiv[1] to Ndiv[4] simultaneously reaching the four 2 / 3 frequency dividers, the output signal CLK1 of one of the 2 / 3 frequency dividers is used to trigger D flip-flops DFF1 to DFF4. At the same time, in order to eliminate the noise accumulation of the frequency divider, the output signal of the high-frequency frequency divider is used to trigger D flip-flop DFF5 to generate the final frequency division signal DIV.

[0067] The low-jitter, low-reference-spurious orthogonal subsampling PLL of this invention is designed using a standard 28nm CMOS process and has undergone post-simulation verification. With a 0.9V power supply, a reference clock frequency of 250MHz, a bandwidth of 12.5MHz, and an output signal frequency range of 10 to 11.5GHz, the overall power consumption of the orthogonal subsampling PLL at an output frequency of 10.5GHz is 12.9mW, the root mean square jitter is 43.6fs, the reference spurious is -102dBc, and the lock time is 500ns. The phase-locked loop quality factor (FoMJ) is -256.1dB, and the chip core area is 0.72mm².

[0068] like Figure 10 As shown, integrating the output phase noise over a frequency offset range from 1 kHz to 100 MHz yields a root mean square jitter of 43.6 fs. The spectrum of the output signal is shown below. Figure 11 As shown, the reference spurious signal at 250MHz is -102dBc. The power decomposition of the orthogonal subsampling PLL is shown in the attached figure. Figure 12 As shown in the attached figure, the control voltage changes over time. Figure 13When the control voltage remains unchanged, it indicates that the orthogonal subsampling PLL is locked, which shows that the locking time of the orthogonal subsampling PLL of the present invention is 500ns.

[0069] Compared to existing orthogonal PLLs, this invention features lower jitter, lower reference spurious emissions, lower power consumption, and a higher quality factor (FoMJ).

[0070] It should be noted that any parts not disclosed or specifically described in this invention are existing technology or conventional configurations, and their specific structures and working principles will not be elaborated further. In this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0071] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. It can be applied to various fields suitable for the present invention. Other modifications can be readily implemented by those skilled in the art. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and examples shown and described herein.

Claims

1. A low-jitter, low-reference-spurious-orthogonal subsampling phase-locked loop (PLL), comprising a subsampling PLL and a frequency-locked loop, wherein the subsampling PLL includes a closed-loop connected reference clock buffer, a gate-isolated subsampling phase detector, a main charge pump array, a low-pass filter, and a functionally multiplexed QVCO, and the frequency-locked loop includes a closed-loop connected differential-to-single-ended converter module, a frequency-to-phase detector with dead time, an auxiliary charge pump array, and a multi-mode divider, characterized in that: The functional multiplexing QVCO is a noise-cycled Class F structure, including two identical noise-cycled I-core Class F VCOs and Q-core Class F VCOs. The I-core Class F VCO and Q-core Class F VCO achieve orthogonal output through cross-coupling of transistor gates. The source of the oscillation transistors of the I-core Class F VCO and Q-core Class F VCO are connected in series with transistors and a sixth-order resonant cavity is set to form a noise-cycled path. The source terminal of the oscillation transistor outputs a signal to a gate-isolated subsampling phase detector. The sampling switch of the gate-isolated subsampling phase detector is isolated from the outputs of the I-core F-type VCO and the Q-core F-type VCO by transistors to suppress binary frequency shift keying effects.

2. The low-jitter, low-reference-spurious-orthogonal subsampling phase-locked loop according to claim 1, characterized in that, Both the I-core F-type VCO and the Q-core F-type VCO have the following structures: The source pole and The source poles are connected. The drain is grounded. Gate capacitor and inductor The left end; Gate capacitor and inductor The right end, The drain is grounded. source terminal The source pole; Gate capacitor and inductor The right end, Gate capacitor and inductor The left end; Drain and capacitor and inductor Connect the left end; Drain and capacitor and inductor Connect to the right end; inductance center tap ,inductance center tap ,inductance center tap ; inductance and inductor Through coupling coefficient Coupling, inductor and inductor Through coupling coefficient Coupling, inductor and inductor Through coupling coefficient To couple; in to All of them are transistors.

3. The low-jitter, low-reference-spurious-orthogonal subsampling phase-locked loop according to claim 2, characterized in that, The connection relationship between the I-core F-class VCO and the Q-core F-class VCO is as follows: Capacitors of Class F VCO with I core The lower end is connected to the Q core F-type VCO. Gate connection, capacitor of I-core F-type VCO The upper part is connected to the Q core F-type VCO. Gate connection; Q-core F-class VCO capacitor The upper part is related to the I-core F-type VCO. Gate connection, capacitance of Q-core F-type VCO The lower end is connected to the I-core F-type VCO. Gate connection.

4. The low-jitter, low-reference-spurious-orthogonal subsampling phase-locked loop according to claim 1, characterized in that, The structure of the gate-isolated subsampling phase detector includes a first structure and a second structure arranged symmetrically. The first structure includes: Drain and source, capacitor The upper end connection, The source pole and drain, capacitor The upper end and connect; gate connection , gate connection ,capacitance The lower end is grounded, capacitor The lower end is grounded; and The public node is ; Drain and Drain, The source connection, The source pole and Drain, The source pole, Drain and capacitor The upper end connection, gate connection ; Drain and Drain, The drain connection, gate connection ; gate connection , The source is grounded; source terminal ; gate and The gates of the functionally multiplexed QVCO are all connected to the Node connections; The second structure has the same connection relationship as the first structure, and the second structure is related to the functionally multiplexed QVCO. Node connections; in, , , , , , , and All of them are transistors.

5. A low-jitter, low-reference-spurious-orthogonal subsampling phase-locked loop according to claim 4, characterized in that, The gate-isolated subsampling phase detector further includes two virtual sampling branches, which are distributed and connected to the first and second structures in the same way. The structure of the virtual sampling branches is as follows: The source pole and Drain and drain connection, Drain and The source pole, The source pole, drain and capacitor The upper end connection, The gate is connected to the clock signal. , gate connection , drain connection The source pole, gate connection , source terminal The drain electrode, gate connection ,capacitance The lower end is grounded; in, to All of them are transistors.

6. The low-jitter, low-reference-spurious-orthogonal subsampling phase-locked loop according to claim 1, characterized in that, The main charge pump array includes multiple sets of main charge pumps connected in parallel, and the structure of the main charge pump includes: power supply Connecting resistors The upper part The source pole, The source and The source, resistor The lower end connects Drain and gate The source is grounded; gate and gate connection, The source is grounded. Drain and The source connection, gate and The gate and node EN are connected. Drain and Gate and drain, gate, The drain connection, Drain and Drain and node I CP connect; The gate is connected to node VP. The gate is connected to node VN. The source pole and The source poles are all with Drain connection; The nodes VP of the multiple main charge pumps are interconnected, the nodes VN are interconnected, and the node I... CP Nodes are interconnected, but there are no connections between nodes EN; in, to All of them are transistors.

7. A low-jitter, low-reference-spurious-orthogonal subsampling phase-locked loop according to claim 6, characterized in that, The number of main charge pumps is 4 to 6.

8. A low-jitter, low-reference-spurious-orthogonal subsampling phase-locked loop according to claim 1, characterized in that, The auxiliary charge pump array includes multiple sets of auxiliary charge pumps connected in parallel, and the structure of the auxiliary charge pumps includes: power supply With resistance The upper part The source pole, The source pole, The source connection, resistor The lower end and drain and gate, gate, Drain and Gate connection; The source pole, The source pole, The source and The sources are all grounded. Drain and drain and gate, Drain, gate connection, gate and The gates of all are connected to node EN; Drain and Drain, Drain, The source pole, The source connection, gate, gate, gate, The gates are all connected to the node connect; Drain and The source pole, The source pole, Drain, The drain connection, gate, gate, gate, The gates are all connected to the node connect; Drain and The source pole, The source of the extreme, The drain connection, Drain and The source pole, The source pole, Drain connection; Nodes of multiple auxiliary charge pumps They are interconnected, nodes They are interconnected, node I CP1 Nodes are interconnected, but there are no connections between nodes EN; in, to All of them are transistors.

9. A low-jitter, low-reference-spurious-orthogonal subsampling phase-locked loop according to claim 8, characterized in that, The number of auxiliary charge pumps is 2 to 4.

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