145 results about "Effective number of bits" patented technology

A process for reducing the context memory requirements in a processing system is provided by a generic, lossless, compression algorithm applied to multiple tasks or multiple instances running on any type of processor. The process includes dividing data in a task of a multi-tasking system into blocks with each block containing the same number of words. For the data in each task, a word in a block having a maximum number of significant bits is determined, a packing width to the block of said maximum number of significant bits is assigned, and the least significant bits of each word in the block into a packed block of the packing width multiplied by a total number of words in the block is encoded with a lossless compression algorithm. A prefix header at the beginning of each packed block to represent a change in the packing width from the packed block from a packing width of a previous packed block is also provided.

Clock signals are supplied, with a phase shift of 1/n cycles between adjacent clock signals. A data acquisition unit acquires serial data at a timing of each of the clock signals. A phase detection unit detects the phase of the transition edge of the serial data using n bits of data. An effective bit number determination unit determines the effective bit number, which is the number of bits to be acquired, based upon the phase of the transition edge of the serial data in the current data-bit acquisition step and the phase of the transition edge of the serial data in the previous data-bit acquisition step. A data-bit output unit outputs the effective bit number of the bits of data acquired at a timing of each clock signal having a predetermined phase relation with the transition edge of the serial data.

An object of the present invention is to provide a method for encoding signals by separating a signal by using a common multiplier so as to improve the efficiency of compression of audio signals and a method for calculating a common multiplier of a set of numeric values including errors. A common multiplier A, of the input signal samples x(i) in each frame is estimated. Each sample x(i) is divided by A, the quotient is rounded to the number of significant digits, and the rounded quotient y(i) is encoded. The quotient y(i) is multiplied by A and the product is subtracted from x(i) to obtain an error signal z(i), which is then encoded. The multiplier A is encoded and the code of y(i), the code of z(i), and the code of A are combined together and outputted. To estimate the common multiplier, each numeric value is divided by a determined representative value. Irreducible fractions between the maximum positive error and the maximum negative error are obtained by dividing each numeric value by a correct representative value using rational approximation. Among the obtained irreducible fractions, the one having the smallest common denominator of the numeric values is obtained and the common denominator is corrected using the representative value to obtain a common multiplier.

An image compressor has an input pixel value correction unit, a predicted pixel value generation unit, an error level detection unit, a predicted error computation unit, a predicted error coding unit, a packing unit and a target code amount difference level detection unit. The predicted error coding unit encodes, by variable-length coding, group information indicating a group to which the magnitude of a predicted error belongs and added bit data indicating a particular predicted error value in the group, and performs encoding by removing less significant bit data according to a target code amount difference level in the added bit data for the predicted error if the magnitude of the predicted error is equal to or larger than a predetermined value.

The invention relates to a pipeline analog-to-digital converter and a quick calibration method of capacitance mismatch thereof. The quick calibration method is characterized by carrying out inverted order calibration from a level circuit module of the last level. The calibration method of the level circuit module of each level comprises the following steps of: 1. starting calibration: closing thesecond transfer switch and the fourth transfer switch and cutting off the first transfer switch and the third transfer switch to enable the level circuit modules to work in the calibration state; 2. measuring quantitative results: setting input signals for the level circuit modules, and carrying out analog-to-digital conversion by the level circuit modules following the corresponding level and the back analog-to-digital conversion module of the pipeline analog-to-digital converter to obtain a set of corresponding quantitative results; and 3. measuring quantitative step length: subtracting thecorresponding quantitative results to obtain the actual quantitative step length of the level circuit modules and storing the step length in a storage module. Roughly quantitative calibration resultsare added by the invention, thereby improving the linearity of the transmission function of the pipeline analog-to-digital converter and increasing the significant digit of analog-to-digital conversion.

The invention discloses a calibration system and a calibration method suitable for a current source array in a multichannel sectional type current steering DAC (digital to analog converter). The calibration method suitable for the current source array in the multichannel sectional type current steering DAC includes steps: firstly, calibrating a channel, and then sequentially calibrating other channels, and enabling output among all the channels to tend to be uniform, wherein when the channels are calibrated, switches in a current source switch array are by selectively closed and calibrated, and an output amplitude adjustment circuit is adjusted so as to sequentially calibrate a low data bit segment and a high data bit segment of the current source array segment by segment. The calibration method suitable for the current source array in the multichannel sectional type current steering DAC can calibrate each current source at the low data bit segment of the sectional type current steering DAC, and thereby achieves high calibration accuracy, remedies deviation and a mismatch, among the current sources in the current source array of the sectional type current steering DAC, improves linearity of the single DAC, and then improves performance indexes such as the significant number of digits of the DAC and a spurious free dynamic range, and improves linear performance of the multichannel sectional type current steering DAC and amplitude consistency among all the channels.

An analog-to-digital converter (ADC) of a radio receiver can consume a relatively large amount of power. It is typically desirable to minimize power consumption, particularly with battery-powered devices, such as in wireless receivers. In certain conditions, the effective number of bits (ENOB) required from an ADC of a receiver can vary. The power consumption of certain ADC topologies, such as pipelined converter topologies, can vary with the number of bits. One embodiment dynamically varies the ENOB of an ADC to more optimally consume power. This can extend battery life.

The invention provides an orthogonal frequency division multiplexing receiving system and an automatic gain control method. The antenna of the system is connected with a band-pass filter, a radio frequency gain amplifier, an orthogonal demodulator, a baseband gain amplifier, a first digital-to-analog converter, a decoder, a frame alignement judging device, an automatic gain controller, a signal power processor, a second digital-to-analog converter, a ogarithmic detector, a band-pass filter in turn, wherein the automatic gain controller is respectively connected with the baseband gain amplifier, the radio frequency gain amplifier, while the first digital-to-analog converter is connected with the frame alignement judging device. The gain control method is that the receiver carries the logarithm demodulation on the received signals, to control the system gain according to the power detecting result and the state of the two modules of frame synchronization and the decoder, to reach the aim of correctly adjusting the system gain. The invention has high detecting precision, small computation complexity, short response time, which is suitable to orthogonal frequency division multiplexing receiving system and can effectively increase the significant figure of the analog-to-digital converter.

The invention provides an oversampling 64-time sigma-delta modulation circuit with an effective bit being 18. The circuit comprises an interpolation filter and a sigma-delta modulator. The interpolation filter is used for conducting oversampling interpolation and filtering on digital input signals. The input end of the sigma-delta modulator is connected with the output end of the interpolation filter, the sigma-delta modulator is used for modulating oversampled digital signals, shaping quantized noise introduced by a quantizer, moving noise in the signal bandwidth out of the bandwidth, and meanwhile guaranteeing that transmission of the signals is not affected, and output 1-bit 0/1 code streams need to be restored through a backward-stage analog reconstruction filter so as to acquire analog signals. An improved structure is adopted in a half-band filter in the interpolation filter so that the area of the half-band filter can be greatly reduced; for the sigma-delta modulator, a monocycle high-order structure easier to achieve is adopted, the stability problem is analyzed, the high signal to noise ratio is achieved, and meanwhile stability of the modulator is guaranteed.

The invention, which belongs to the technical field of the analog integrated circuit, provides a front-end calibration method for an assembly line ADC. Correction is carried out by starting with a first-stage gain of an assembly line ADC until completion of a previous (N-1)th-stage gain of the assembly line ADC to realize front-end calibration once. When the gains from the first stage to the (N-1)th stage are obtained, an error between a restored signal and an original signal is obtained. Before calibration, an analog output of the previous (N-1)th stage of the assembly line ADC is obtained by using a digital output of a flash memory type ADC. During the calibration process, the gain at each stage of the assembly line ADC is searched based on an MATLAB program; the output data are stored of the assembly line ADC and a fast fourier transform analysis is carried out on the restored signal; and when indexes like an effective bit number meet requirements, gain searching is determined to be corrected to realize assembly line ADC calibration. Therefore, a defect of low traditional calibration precision in the high-speed high-precision assembly line ADC is overcome; rapid, correct and high-efficiency calibration is realized; and the front-end calibration method is suitable for calibration of a high-speed high-precision assembly line ADC.

OLT is provided with a field for storing the number of effective bits for searching ONU serial numbers, a field for storing a search start serial number and a field for storing a search end serial number, and ONU serial numbers are searched from the search start serial number to the search end serial number within the number of effective bits to automatically perform acquisition of the ONU serial number and ONU connection. An ONU automatic connection method for an ATM-PON system is provided by which an ONU serial number is searched efficiently without registering the ONU serial number from OpS to OLT.

The method for high-speed modulo multiplication is a method for multiplying integers A and B modulus N that is optimized for high speed implementation in an electronic device, which may be implemented in software, but is preferably implemented in hardware. The multiplication is performed on devices requiring no more than k+2 bits, where k is the number of significant bits in A, B, and N. The method computes the running product b_iiAW, where AW is either A when the previous running product is negative, or W when the previous running product is positive, W being the N-conjugate of A formed by A−N. On each iteration, the magnitude of the running product is reduced by a scaling factor no greater than 2N according to the state of the two most significant bits of the running product when carry propagate adders are used.

An example embodiment provides a method, comprising: storing pre-calculated quantisation error data relating to a data quantisation process; receiving data to be quantised; quantising the data to reduce the number of significant bits thereof; and determining a quantisation error for the quantised data from the pre-calculated quantisation error data.

A single ADC acquisition channel dynamic characteristic test method belongs to the field of electronic measurement. The test flow comprises steps of sampling the excitation signals to obtain an observation sample; determining the frequency search boundary and the frequency selection point, calculating the least squares residual corresponding to the frequency selection point, and determining the model of the base frequency signal; estimating the signal to noise ratio SINAD and the effective number of bits ENOB; constructing the residual sequence matrix, calculating the covariance matrix, performing the feature decomposition, searching and calculating the harmonic frequency in the neighborhood of the corresponding peak, and estimating the harmonic amplitude; and estimating the signal non-harmonic ratio SNHR, the spurious-free dynamic range SFDR and total harmonic distortion THD. The method firstly adopts a method of combining time-frequency domain analysis and spatial spectrum analysis, can accurately estimate the excitation signal, the noise component and the harmonic distortion component contained in the observation sample, and can effectively improve the spectrum leakage and fence effect in the spectrum analysis. The estimation is highly precise, the calculating amount is small, and the hardware implementation is easy.

The invention provides an optical analog-to-digital converter based on polarization modulation, belonging to the field of photoelectric technology, and relates to a photoelectric signal processing and optical analog-to-digital converter. N-path current modulation signals uniformly divided by a sampling analog current signal are respectively input to a magnetic induction coil by an amplifying circuit; pulsed light emitted by a laser is polarized into a linearly polarized light by a polarizer, and the linearly polarized light is divided into N light path signals by a beam splitter, and the N light path signals are respectively input to N photoelectric branch circuits; the optical signal of each photoelectric branch circuit firstly passes through magneto optic effect material in the magnetic induction coil, and then is analyzed by an analyzer into an optical signal which is converted into an electrical signal by a photoelectric detector, the electrical signal is amplified by an amplifier and is input to the corresponding comparer to carry out threshold value judgment, and a digital signal is finally output by the comparer. The converter can realize the output of the digital signal with the traditional binary code and Gray code, and has the advantages of rapid sampling speed, more effective number bits, no restriction of the binary code and the Gray code, simple structure and low cost.

The invention belongs to the field of optoelectronic technology, and in particular relates to a method and a device for improving the linearity of microwave signal time stretching. The method of the invention utilizes the carrier suppression modulation of the double parallel modulator to realize the suppression of the DC component of the output signal, increases the sensitivity of the detector, effectively eliminates the even-order harmonic distortion, and improves the linearity of the system. By setting the optimal optical power coupling ratio and microwave signal power coupling ratio of the dual parallel modulators, combined with the modulation signal and reference signal interference and balanced detection, the third harmonic and third-order intermodulation distortion can be effectively suppressed, and the system can be significantly improved. The signal-to-noise-distortion ratio and effective number of bits are used to realize the linearization of microwave signal time-stretching analog-to-digital conversion systems.

The invention discloses a successive approximation type analog-digital converter for a monotonic switching mode, belongs to the field of high-speed successive approximation type analog-digital converters, and particularly relates to the field of comparator circuits. The successive approximation type analog-digital converter comprises an electric charge load distribution digital-analog converter, a comparator and a control logic unit. A redundant circuit is added to an electric charge load distribution digital-analog converter in an existing analog-digital converter, and the comparator is detuned and noise is adjusted by adding a tail current source capable of being controlled logically on an existing comparator and adjusting the proportion of tail currents inside different comparison cycles. The successive approximation type analog-digital converter has the advantages of being simple in structure, low in power consumption and high in speed. The 10-digit 100 MS/s verification successive approximation type analog-digital converter designed under the 0.13-micrometer technology can obtain the effective number of bits more than 9.3, the power consumption is only 1.7 mW, and the quality factor can reach 25.7 fJ/conv.

The invention provides a data caching and reproduction system for a time-interleaved analog to digital conversion system. According to the system, in order to improve the data caching accuracy, a high-precision time-interleaved ADC multi-phase clock is designed; moreover, internal resources of an FPGA are utilized fully; the integration complexity and hardware cost of the system are reduced; sample data is reasonably stored; digital rear end compensation is carried out on a bias error, a gain error and a time phase error existing in the TIADC system; and finally data is uploaded to an upper computer. According to a test result, a form of an input signal is restored relatively truly, and the performance such as an SNR (Signal to Noise Ratio) and ENOB (Effective Number of Bits) of the TIADC system is effectively improved through digital rear end compensation.

A concurrent asynchronous USB 2.0 data stream destuffer and separator with variable-width bit-wise memory controller is described. A parallel stream bit destuffer module identifies in parallel one or more stuffed bits in a decoded data field of a received data stream using a six-bit sliding window. The stuffed bits are bits that were inserted into the received USB data stream by a transmitter to force data transitions in the received USB data stream. A data separator module separates the one or more stuffed bits from a plurality of valid data bits in the decoded data field. A memory module generates an incremental pointer value representative of the number of valid bits and writes the plurality of valid data bits from the decoded data field into a variable sized bit-wise memory structure.