Front-end calibration method for assembly line ADC based on minimum quantization error

Abstract

The invention, which belongs to the technical field of the analog integrated circuit, provides a front-end calibration method for an assembly line ADC. Correction is carried out by starting with a first-stage gain of an assembly line ADC until completion of a previous (N-1)th-stage gain of the assembly line ADC to realize front-end calibration once. When the gains from the first stage to the (N-1)th stage are obtained, an error between a restored signal and an original signal is obtained. Before calibration, an analog output of the previous (N-1)th stage of the assembly line ADC is obtained by using a digital output of a flash memory type ADC. During the calibration process, the gain at each stage of the assembly line ADC is searched based on an MATLAB program; the output data are stored of the assembly line ADC and a fast fourier transform analysis is carried out on the restored signal; and when indexes like an effective bit number meet requirements, gain searching is determined to be corrected to realize assembly line ADC calibration. Therefore, a defect of low traditional calibration precision in the high-speed high-precision assembly line ADC is overcome; rapid, correct and high-efficiency calibration is realized; and the front-end calibration method is suitable for calibration of a high-speed high-precision assembly line ADC.

Description

technical field [0001] The invention belongs to the field of analog integrated circuits, and in particular relates to a front-end calibration method of a pipeline ADC based on a minimum quantization error. Background technique [0002] The pipeline ADC structure is as follows figure 1 As shown, the input signal is sent to the pipeline unit ADC after being sampled by the sample-and-hold circuit, and each unit ADC performs sampling and residual amplification alternately under the control of two-phase non-overlapping clocks. Inside the unit ADC, the phase signal is sampled by the multiplication digital-to-analog converter MDAC and sub-ADC at the same time, and the sub-ADC generates a digital code Di by comparison; when maintaining the phase, Di is subtracted from the input signal by MDAC to generate a residual difference, and the MDAC performs residual difference Amplify, the residual difference is amplified and sent to the next stage as the input signal of the next stage. Th...

AI Technical Summary

Problems solved by technology

The traditional MDAC can achieve the high gain requirement of the operational amplifier in the low-speed and low-precision pipeline ADC, so that the MDAC gain Gain is approximately equal to its ideal value, that is, a constant However, with the development of pipeline ADCs towards high speed and high precision, high-speed and high-precision pipeline ADCs have higher and higher requirements for the unit gain bandwidth product of op amps, and high bandwidth and high gain op amps are difficult to achieve, and the gain of MDAC is no longer seemingly equal to a constant As a result, gain error occurs, which brings nonlinearity and affects ADC performance

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