Pipeline analog-to-digital converter and quick calibration method of capacitance mismatch thereof

Abstract

The invention relates to a pipeline analog-to-digital converter and a quick calibration method of capacitance mismatch thereof. The quick calibration method is characterized by carrying out inverted order calibration from a level circuit module of the last level. The calibration method of the level circuit module of each level comprises the following steps of: 1. starting calibration: closing thesecond transfer switch and the fourth transfer switch and cutting off the first transfer switch and the third transfer switch to enable the level circuit modules to work in the calibration state; 2. measuring quantitative results: setting input signals for the level circuit modules, and carrying out analog-to-digital conversion by the level circuit modules following the corresponding level and the back analog-to-digital conversion module of the pipeline analog-to-digital converter to obtain a set of corresponding quantitative results; and 3. measuring quantitative step length: subtracting thecorresponding quantitative results to obtain the actual quantitative step length of the level circuit modules and storing the step length in a storage module. Roughly quantitative calibration resultsare added by the invention, thereby improving the linearity of the transmission function of the pipeline analog-to-digital converter and increasing the significant digit of analog-to-digital conversion.

Description

technical field [0001] The invention relates to an analog-to-digital converter and a calibration method thereof, in particular to a pipelined analog-to-digital converter and a fast calibration method for capacitance mismatch thereof. Background technique [0002] See figure 1 As shown, the existing pipelined analog-to-digital converter samples the input analog signal through the provided sample-and-hold module 100, and performs quantization of the analog-to-digital conversion by several stages of circuit modules 200 in series and the post-analog-to-digital conversion module 300, and each obtained The quantization results of the stages are weighted and added through the digital offset and addition module 400 to output digital signals. [0003] See figure 2 As shown, each stage circuit module 200 is controlled by a two-phase non-overlapping clock. In phase 1, the stage circuit sampling module 230 samples the analog signal input to the stage, and the analog-to-digital conve...

AI Technical Summary

Problems solved by technology

However, the calibration time of this calibration method is long, and as the effective number of digits increases, the calibration time will be extended exponentially

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