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Data caching and reproduction system for time-interleaved analog to digital conversion system

An analog-to-digital conversion and data caching technology, which is applied in the fields of analog-to-digital converter, analog-to-digital conversion, analog/digital conversion calibration/test, etc., can solve the problems of difficult design method, long development cycle and high hardware resource requirements. Achieve the effect of reducing integration complexity and hardware cost, and improving cache accuracy

Inactive Publication Date: 2017-09-01
SUN YAT SEN UNIV +1
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  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

However, this method requires high hardware resources, the design method is relatively difficult, and the development cycle is long, which brings great challenges to system designers.

Method used

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  • Data caching and reproduction system for time-interleaved analog to digital conversion system
  • Data caching and reproduction system for time-interleaved analog to digital conversion system
  • Data caching and reproduction system for time-interleaved analog to digital conversion system

Examples

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Embodiment 1

[0028] The present invention provides a data buffering and reproducing system of a time-interleaved analog-to-digital conversion system such as figure 1 As shown, it consists of a multi-channel ADC module, a multi-phase clock generation module, an asynchronous clock domain data processing module, a data reordering and correction module, and a data sending memory module.

[0029] The principle diagram of high-precision multi-phase clock generation is as follows: figure 2 shown. The data reception of the TIADC system needs to be sequentially driven by the multi-phase clock. In order to obtain the accurate multi-phase drive clock of the data buffer unit, the PLL frequency multiplication technology is used to obtain a high-stability clock signal, and the internal register of the CLOCK GENERATE module is configured through SPI. Realize fine-tuning Δt of clock delay 1 , Δt 2 , Δt 3 , Δt 4 , since the internal time adjustment accuracy of the module is related to the minimum uni...

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PUM

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Abstract

The invention provides a data caching and reproduction system for a time-interleaved analog to digital conversion system. According to the system, in order to improve the data caching accuracy, a high-precision time-interleaved ADC multi-phase clock is designed; moreover, internal resources of an FPGA are utilized fully; the integration complexity and hardware cost of the system are reduced; sample data is reasonably stored; digital rear end compensation is carried out on a bias error, a gain error and a time phase error existing in the TIADC system; and finally data is uploaded to an upper computer. According to a test result, a form of an input signal is restored relatively truly, and the performance such as an SNR (Signal to Noise Ratio) and ENOB (Effective Number of Bits) of the TIADC system is effectively improved through digital rear end compensation.

Description

technical field [0001] The invention relates to the field of digital signal processing, more specifically, to a data buffering and reproducing system of a time-interleaved analog-to-digital conversion system. Background technique [0002] With the rapid development of microelectronics technology, the integration and complexity of circuit systems continue to increase, and strict requirements are placed on speed. In some high-end instrumentation, medical equipment, radar, communications and other fields, analog front-end data The acquisition speed needs several Gsps or even tens of Gsps. Due to internal thermal noise, aperture jitter, and uncertainty of transit time, monolithic integrated high-speed sampling technology faces mutual constraints on accuracy and speed, and multi-channel time-interleaved analog-to-digital conversion technology can make up for this defect. However, in the hardware implementation process of the high-speed time-interleaved analog-to-digital conversi...

Claims

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Application Information

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IPC IPC(8): H03M1/12H03M1/10
CPCH03M1/1009H03M1/121H03M1/1245
Inventor 谭洪舟蔡彬李宇刘崇庆吕立钧农革
Owner SUN YAT SEN UNIV
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