The invention provides a c code and
verilog code generation method and device, and relates to the technical field of
software development and FPGA board card debugging. When the method is executed, firstly, a model is built through GCKontrol
modeling software, secondly, floating-point
simulation is conducted on the model, thirdly, subsystem packaging is conducted on a module, needing to automatically generate the
verilog code, in the model, then the module, needing to automatically generate the
verilog code, in a subsystem is calibrated according to a floating-point
simulation result, then, the calibrated model is simulated, and finally, the model is subjected to automatic generation of the
verilog code. And finally, if the
simulation result of the model accords with the expectation, generating a c code and a
verilog code at the same time by utilizing the calibrated model. In this way, the c code and the
verilog code are automatically generated at the same time.