Reset circuit test system and method for logic built-in self-test

Abstract

A logic built-in self-test reset circuit test system comprises a test vector generator, a logic built-in self-test controller and a test response analyzer, the test vector generator generates a reset test vector and a pseudo-random test vector, receives an instruction of the logic built-in self-test controller, and analyzes the reset test vector and the pseudo-random test vector according to the instruction of the logic built-in self-test controller. The reset signal, the clock signal, the scanning enable signal and the scanning vector output signal are output to a circuit to be tested; the logic built-in self-test controller is used for respectively controlling the signal output of the test vector generator and controlling the test response analyzer to test the circuit to be tested; and the test response analyzer receives an instruction of the logic built-in self-test controller and tests the circuit to be tested. The invention also provides a reset circuit test method for logic built-in self-test, which solves the problem that the reset signal cannot be highly covered in the traditional logic built-in self-test by using less logic, and improves the fault coverage rate.

Description

technical field [0001] The invention relates to the technical field of integrated circuit board-level testing, in particular to a reset circuit testing system and method for logic built-in self-testing. Background technique [0002] With the shrinking of the process size of the integrated circuit and the improvement of the chip scale, higher requirements are put forward for the difficulty of chip testing, the testing cost and the testing method. It has become a major issue in chip testing to achieve higher test coverage with less test cost and less test time. [0003] Traditional chip testing will be performed on automatic test equipment (ATE) for memory cell built-in self-test (MBIST) for on-chip memory, for boundary scan test (BSD) for system pin processing module (IO PAD), for digital logic Scan chain testing (SCAN), quiescent current based testing (IDDQ), low voltage testing at reduced supply voltage, testing for analog circuits, etc. These are tests before the chip le...

AI Technical Summary

Problems solved by technology

The test is also performed through pseudo-random test vectors, but due to the uncertainty of the test vectors, there is a lack of coverage of this type of registers, which reduces the fault coverage

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