Low-power consumption weighted pseudo-random test method, system, device and storage medium

Abstract

The present invention provides a low-power consumption weighted pseudo-random test method, a low-power consumption weighted pseudo-random test system, a low-power consumption weighted pseudo-random test device and a storage medium. The test method includes the following steps that: a scan forest is established; all scan chains controlled by the same multi-output selector are all set in be the same scan chain subset; weight assignment is performed on test enable signals in each scan chain subset according to a testability gain function; the scan forest is adopted to perform a pseudo-random test, and a pseudo-random test vector is outputted; and a pseudo-random test result is calculated according to the pseudo random test vector. The fault coverage rate of the test method and test system is high and is 20% higher than the fault coverage rate of a traditional method; the low hardware overhead of the test method and test system is low, no additional delay overhead being brought about; the structure of the test method and test system is simple, so that the test method and test system can be widely applied to the industrial community, can be easily embedded into an existing EDA tool, and can support pseudo-random testing and deterministic self-testing; and combined with the deterministic self-testing, the test method and test system can effectively reduce test data capacity.

Description

technical field [0001] The invention relates to the technical field of integrated circuit delay test testability, in particular to a low power consumption weighted pseudo-random test method, system, equipment and storage medium. Background technique [0002] As the circuit scale increases, the gap between functional and test power consumption becomes wider. With the increase of energy consumption, the problem of chip overheating also appeared. Overheating of the chip will shorten the life of the product. Now some more accurate power consumption models have been proposed. One is a fast simulation method for the external interconnect design of low-power chips, and the other is the stacked IC design for the important TSV modeling / simulation technology for low-power 3D networks. However, scan-based self-test techniques (BIST) have higher power consumption than deterministic scan tests due to the increased random code switching activity. [0003] Recent research methods have ...

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Problems solved by technology

But these methods usually result in more energy consumption due to frequent flip-flop scans

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