Prediction of branch instructions in a data processing apparatus

Abstract

The present invention provides a data processing apparatus and method for predicting branch instructions in a data processing apparatus. The data processing apparatus comprises a processor for executing instructions, a prefetch unit for prefetching instructions from a memory prior to sending those instructions to the processor for execution, and branch prediction logic for predicting which instruction should be prefetched by the prefetch unit. The branch prediction logic is arranged to predict whether a prefetched instruction specifies a branch operation that will cause a change in instruction flow, and if so to indicate to the prefetch unit a target address within the memory from which a next instruction should be retrieved. The instructions include a first instruction and a second instruction that are executable independently by the processor, but which in combination specify a predetermined branch operation whose target address is uniquely derivable from a combination of attributes of the first and second instruction. The data processing apparatus further comprises target address logic for deriving from the combination of attributes the target address for the predetermined branch operation, the branch prediction logic being arranged to predict whether the predetermined branch operation will cause a change in instruction flow, in which event the branch prediction logic is arranged to indicate to the prefetch unit the target address determined by the target address logic. Accordingly, even though neither the first instruction nor the second instruction itself uniquely identifies the target address, the target address can nonetheless be uniquely determined thereby allowing prediction of the predetermined branch operation specified by the combination of the first and second instructions.

Description

[0001] 1. Field of the Invention[0002] The present invention relates to techniques for predicting branch instructions in a data processing apparatus.[0003] 2. Description of the Prior Art[0004] A data processing apparatus will typically include a processor core for executing instructions. Typically, a prefetch unit will be provided for prefetching instructions from memory that are required by the processor core, with the aim of ensuring that the processor core has a steady stream of instructions to execute, thereby aiming to maximise the performance of the processor core.[0005] To assist the prefetch unit in its task of retrieving instructions for the processor core, prediction logic is often provided for predicting which instruction should be prefetched by the prefetch unit. The prediction logic is useful since instruction sequences are often not stored in memory one after another, since software execution often involves changes in instruction flow that cause the processor core to ...

AI Technical Summary

Problems solved by technology

However, this can impact on performance, since it requires the use of other instructions to ensure that the appropriate offset value is placed in the required register prior to execution of the branch instruction.

Furthermore, in the context of prediction, it means that the prediction logic is typically unable to make any prediction on such a branch instruction, since it will typically not have access to the contents of the register specified within the branch instruction, and accordingly cannot make any prediction of the target address.

However, as mentioned above, the instructions of certain instruction sets do not have enough bits available to enable the target address (or the offset value) to be specified.

However, in Reduced suction Set Computer (RISC) based systems, the basic design principle is that the instructions should all be of the same length, since variable length instructions add significantly to complexity.

When specifying a branch instruction in 16 bits, there is typically insufficient space to specify the target address (or offset va

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