The invention provides an IEEE (Institute of Electrical and Electronic Engineers) 1149.10 to IEEE 1500 (Institute of Electrical and Electronic Engineers)
signal The method specifically comprises the steps that a CONFIG packet, a TARGET packet, a CH-SELECT packet and an SCAN packet based on the IEEE Std 1149.10-2017 standard are received, after equipment configuration, target selection and channel locking are sequentially completed, the SCAN packet is decoded according to the IEEE 1149.10 rule, an IEEE1500 driving
signal is generated by combining the mapping relation between a scanning channel and IEEE1500 registers (WIR, WBR and WBY), and
communication control over the IEEE1500 interface
chip equipment is achieved. Wherein the IEEE1500 driving
signal covers a Wrapper
clock signal (WRCK), a Wrapper serial input signal (WSI), an instruction /
data selection signal (SelectWIR), a shift
control signal (ShiftWR) and an update
control signal (Update WR), and the IEEE1500 driving signal comprises a Wrapper
clock signal (WRCK), a Wrapper serial input signal (WSI), an instruction /
data selection signal (SelectWIR), a shift
control signal (ShiftWR) and an update control signal (Update WR). According to the method, IEEE 1149.10 data packet interaction and
time sequence constraints are followed, after
test data are coded to generate a compliance packet, an IEEE1500 driving signal with an accurate
time sequence can be generated through conversion, the
data analysis and
test requirements of a high-
speed test port are met, and an efficient solution is provided for
embedded core test of a
system-on-
chip (SoC).