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Virtual test bus circuit for network-on-chip system and test method thereof

A network-on-chip, virtual test technology, applied in transmission systems, digital transmission systems, data exchange networks, etc., can solve the problems of the connection is not effectively used, can not effectively reduce the test time, etc., to achieve easy test data broadcast, eliminate Redundant test time, the effect of reducing test time

Active Publication Date: 2009-11-25
INST OF COMPUTING TECH CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] 2. Usually, the number of scan chains in the system is always less than the bandwidth of the system channel, so some connections are not effectively used in the process of channel transmission of test data
However, in the traditional unicast network, the broadcast mechanism is implemented by retransmission, so it cannot effectively reduce the test time

Method used

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  • Virtual test bus circuit for network-on-chip system and test method thereof
  • Virtual test bus circuit for network-on-chip system and test method thereof
  • Virtual test bus circuit for network-on-chip system and test method thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0056] like Figure 5 As shown, the figure is an example of a router module after design for testability, in which modules 4, 7, and 9 are modules added by design for testability.

[0057] The router contains 5 sets of input and output ports, namely east, south, west, north, and core. Corresponding to each group of input ports, the system is configured with an input control circuit module 3 and a corresponding testability module—the input control circuit bypass module 4 . According to the test enable signal ten, the multiplexer module 9 selects the output of the input control circuit module 3 as the final output signal in the working state, and selects the output of the input control circuit bypass module 4 as the final output in the test state. Signal.

[0058] Each router module includes a routing logic module 6. In order to generate a virtual test bus, a test control module 7 is added to the routing logic module 6 in this embodiment. According to the values ​​of the test...

Embodiment 2

[0062] The invention also provides a test method based on the virtual test bus circuit for the on-chip network system. The main design of this test method has two aspects, on the one hand, by generating routing control signals by the information forwarding module 5 during testing, and connecting each router module 1 according to the routing control signals, forming a plurality of virtual test buses, thereby achieving The purpose of improving the utilization efficiency of original connection resources of the network-on-chip system. Another aspect is to eliminate the redundant time caused by the protocol by gating the input control circuit bypass module 4 during the test.

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Abstract

The invention provides a virtual test bus circuit for a network-on-chip system and a test method thereof. The virtual test bus circuit comprises a plurality of router modules which are connected with each other; each router module comprises an input control circuit module and an information forwarding module; and the information forwarding module generates a routing control signal for testing data when the network-on-chip system is in a test state, and forwards the data to other router modules or embedded cores. The test method comprises the steps of: 1) setting a test enable signal of a chip as valid; step 2) generating the routing control signal by the information forwarding module and forming a plurality of virtual test buses; and step 3) externally outputting a test vector, and implementing the test on the embedded cores through the virtual test buses. The virtual test bus circuit and the test method can eliminate redundancy time caused by protocols, and can better utilize existing interconnection resources of the network-on-chip system, thereby effectively improving the test efficiency and shortening the test time.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, in particular, the invention relates to a test circuit and a test method in chip testability design technology. Background technique [0002] With the advancement of integrated circuit technology, more and more cores are integrated on the chip, and the traditional bus-based architecture can no longer meet the needs of system bandwidth and scalability. Such as figure 1 As shown, for these problems, network-on-chip (NoC)-based architectures are widely studied and recognized. The router module in the network on chip system is the core of the system. Such as figure 2 As shown, the router of the network on chip system includes an input control module 3 and a message forwarding module 5 . The input control module 3 is used to receive data and interact with the surrounding modules, so related protocols need to be implemented. The message forwarding module 5 is used to generate a routing si...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/26
Inventor 付斌章韩银和李华伟李晓维
Owner INST OF COMPUTING TECH CHINESE ACAD OF SCI
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