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Embedded core wrapper device and design method thereof

An embedded, core-core technology, applied in the field of system-on-chip modular testing

Active Publication Date: 2015-12-30
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] This application provides an embedded core test shell device and its design method, the purpose of which is to solve the problem of how to improve the reusability of the test shell device

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  • Embedded core wrapper device and design method thereof
  • Embedded core wrapper device and design method thereof
  • Embedded core wrapper device and design method thereof

Examples

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Embodiment Construction

[0065] The core test shell structure stipulated by the IEEEStd1500 standard consists of a test shell boundary register (WrapperBoundaryRegister, WBR), a test shell bypass register (WrapperBypassRegister, WBY), a test shell instruction register (WrapperInstructionRegister, WIR), a test shell serial port (WrapperSerialPort, WSP ) and an optional test shell parallel port (WrapperParallelPort, WPP).

[0066] Among them, WBR is a data register, which is used to provide test stimulus and receive test response. WBR is composed of serially connected test shell boundary register unit (WBRCell). WBRCell can realize the application of test stimulus and capture of test response, so as to realize the control and observation of the embedded core. Each input and output port of the embedded core has a WBRCell, but the test access mechanism (TestAccessMechanism, TAM) port and the analog port may not be provided with a WBRCell. IEEEStd1500 only defines two types of WBRCell: input WBRCell and o...

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Abstract

The embodiment of the invention discloses an embedded core wrapper device which comprises a wrapper instruction register (WIR), a wrapper boundary register (WBR), a wrapper bypass register (WBY), a multiplex select generator (MSG), a first multiplex and a second multiplex, wherein the MSG generates a multiplex selection signal sequence according to the sequence of control signals outputted by the WIR, and outputs the multiplex selection signal sequence to a corresponding multiplex (MUX) in the WBR in a mapping manner according to a preset mapping rule; the mapping rule is set according to the mode of connection between WBR units in the WBR and each MUX as well as function of each MUX. Therefore, when the WBR connection mode is changed, MUX functions, MUX input signal connection and the position of each MUX in a wrapper scanning chain are analyzed according to a new WBR, and the embedded core wrapper device of which the MSG mapping rule is regenerated is applicable to the new WBR.

Description

technical field [0001] The present application relates to the field of system-on-chip (System-on-Chip, SoC) modular testing, in particular to an embedded core testing shell device and a design method thereof. Background technique [0002] With the advancement of integrated circuit technology and the continuous improvement of people's requirements for integrated circuit performance and time-to-market, system-on-chip technology has become the development trend and technical mainstream of today's integrated circuits. The core of SoC technology is the multiplexing of embedded cores. The multiplexing of embedded cores is not only the multiplexing of circuit logic, but also the test multiplexing of embedded cores. When the embedded core is integrated into the SoC, its input and output ports are also embedded in the SoC, so the originally controllable and measurable ports become uncontrollable and unobservable. Therefore, a new test architecture and test method are needed to solve...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28
Inventor 冯燕陈岚王东
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI