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Integrated circuit packaging method with postpositional embedded core flow and package structure

A technology of integrated circuits and packaging methods, which is applied in the direction of circuits, electrical components, and electric solid devices, and can solve the problems of reduced compactness of integrated circuits, increased manufacturing process steps, and reduced production yields, so as to improve the heat dissipation performance of chips and simplify The production process and the effect of improving electrical performance

Active Publication Date: 2019-04-19
NANTONG ACCESS SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this method has the following disadvantages: firstly, many manufacturing process steps will be added, thereby increasing the manufacturing cost; secondly, because the substrate structure obtained by this method is more complicated, the manufacturing yield is lower In the third aspect, due to the increase of the substrate thickness, the overall compactness of the packaged integrated circuit will decrease, which is not conducive to the miniaturization design of the package.

Method used

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  • Integrated circuit packaging method with postpositional embedded core flow and package structure
  • Integrated circuit packaging method with postpositional embedded core flow and package structure
  • Integrated circuit packaging method with postpositional embedded core flow and package structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0075] This embodiment provides an integrated circuit packaging method and its corresponding packaging structure after the buried core process.

[0076] In this example, if figure 1 As shown, a post-buried integrated circuit packaging method includes the following steps:

[0077] S1 , making a semi-finished board 100 , and disposing device pads 103 for electrically connecting active and / or passive devices 200 on the semi-finished board 100 . In the packaging method of the present invention, the semi-finished board 100 is first produced. The semi-finished board 100 is generally a packaging structure located under the active and / or passive device 200. The semi-finished board 100 can be a single-layer board structure or a multi-layer board structure. Such as figure 2 As shown, the semi-finished board 100 of this embodiment is a single-layer board structure, including a packaging material 101, and the packaging material 101 is provided with conductive copper pillars 102 (electr...

Embodiment 2

[0112] This embodiment provides an integrated circuit packaging method and a corresponding packaging structure after the component embedding process.

[0113] In this example, if Figure 10 As shown, the integrated circuit packaging method after the component embedding process includes the following steps:

[0114]P1 , making a semi-finished board 100 , and disposing device pads 103 for electrically connecting active and / or passive devices 200 on the semi-finished board 100 . In the packaging method of the present invention, the semi-finished board 100 is first produced. The semi-finished board 100 is generally a packaging structure located under the active and / or passive device 200. The semi-finished board 100 can be a single-layer board structure or a multi-layer board structure. Such as Figure 11 As shown, the semi-finished board 100 of this embodiment is a single-layer board structure, including a packaging material 101, and the packaging material 101 is provided with c...

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Abstract

The present invention discloses an integrated circuit packaging method with a postpositional buried core flow and a package structure. A multi-layered board is formed by firstly adding layers, then atrench body is etched to embed active and / or passive devices, and then the sealing process is performed, thereby effectively simplifying the manufacturing process. In the second aspect, the advantagesof lead bonding and flip-chip bonding are compatible to cancel to a metal wire or a tin shot in the lead bonding and the flip-chip bonding and reduce the production cost; in the third aspect, the active and / or passive devices are inlaid in the package and are in seamless connection with the package material to improve the electrical performance, improve heat dissipation performance of the chip, achieve the package volume, shorten the connection with the outside, and allow the package size to be lighter and thinner. The integrated circuit packaging method with the postpositional buried core flow and the package structure can be widely applied to various integrated circuit package.

Description

technical field [0001] The invention relates to the field of system level packaging, in particular to a packaging method and packaging structure of a buried core substrate. Background technique [0002] Integrated circuit packaging: put the integrated circuit die (Die) and passive devices (resistors, capacitors, etc.) produced by the fab on a substrate that acts as a load-bearing function, lead out the pins, and then fix and package them into a package. overall. [0003] Consumer electronics, such as computers and telecommunications equipment, are becoming increasingly integrated, driven by the need for miniaturization of increasingly complex electronic components. The overall drive for the evolution of integrated circuits involves making smaller, thinner, lighter and more powerful products in high-reliability packages. The overall requirements for this packaged product are high reliability and proper electrical performance, thinness, rigidity, flatness, good thermal perfo...

Claims

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Application Information

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IPC IPC(8): H01L21/48H01L21/56H01L21/60H01L23/31H01L23/367H01L23/498
CPCH01L23/49827H01L23/49838H01L24/81H01L21/4817H01L21/486H01L21/563H01L23/3114H01L23/3128H01L23/3677H01L2224/81986H01L2224/81365H01L2224/16225H01L2224/24
Inventor 陈先明冯磊周勇胜
Owner NANTONG ACCESS SEMICON CO LTD
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