17 results about "Interrupt vector table" patented technology

The invention discloses an online upgrading method for a single-chip microcomputer with codes running in an RAM (random access memory) without resetting, and relates to the technical field of embedded software, a flash memory is divided into two storage areas, and the RAM is divided into a variable area, two interrupt vector table areas and two code areas. When the single-chip microcomputer is powered on, codes run in the first flash memory storage area and the first RAM code area. And after receiving the upgrade package, writing the upgrade package into the second flash memory storage area. After upgrading is finished, the RAM area of the second flash memory storage area is processed and migrated to the second RAM code area, meanwhile, the interrupt vector table is processed and migrated to the second RAM interrupt vector table area, and new firmware codes are stored in the second flash memory storage area, the second RAM code area and the second RAM interrupt vector table area. And then exchanging codes of the first flash memory area and the second flash memory area, and pointing an interrupt vector table pointer to a second RAM interrupt vector table area, thereby realizing real-time updating of firmware of the flash memory area and the RAM area of the single-chip microcomputer without resetting.

The invention discloses a self-checking method and device for a storage module, a chip, a medium and a product, and the method comprises the steps: obtaining a pre-established first interrupt vector table from a target storage module when a self-checking program is executed on an error-injected storage module and if a trigger instruction error correction error of the error-injected storage module is detected, the target storage module is not injected with errors; and executing an interrupt service program corresponding to the first interrupt vector table. Therefore, when an instruction error correction error occurs, the interrupt vector table is read from the non-error-injected storage module instead of being read from the error-injected memory, so that a CPU (Central Processing Unit) can be prevented from accessing an invalid interrupt vector table to enter a locking state, and a self-checking program can normally run.

The application discloses an online upgrading method of a multi-core microcontroller starting guide program, and the PC pointer is pointed to the RAM before erasing and writing the FLASH, and the B core is put to sleep and waits for the instruction; when the A core has an upgrading request, the B core receives the IPC interrupt request, the PC pointer jumps to the storage area of the interrupt vector table, the corresponding IPC interrupt service function address is searched, the corresponding upgrading service processing is executed, the PC pointer jumps back to the RAM after the execution is completed, the PC pointer is prevented from pointing to the invalid address, and thus the B core is prevented from abnormally stopping and the starting guide program upgrading operation is successfully completed.

This invention proposes a firmware update method for a controller with a master-slave board design, relating to the technical field of controller firmware updates. It adds a version identifier and version information to the end of the interrupt vector table in the firmware source code, which is simple, convenient, accurate, and universally applicable. It utilizes a large-capacity non-volatile memory on the motherboard and introduces a dual backup mechanism to prevent firmware update failures from causing the controller to be unable to run the RTS firmware. The host computer caches the firmware in the motherboard's non-volatile memory, and the slave board pulls the version from the motherboard's non-volatile memory, reducing the complexity of the firmware update process. For ease of management, an RTS package generator is used to package an RTS firmware package containing all RTS firmware for both the master and slave boards, and integrity verification information is added. The master and slave board bootloaders synchronize the RTS firmware version from the RTS firmware package cached in the non-volatile memory, achieving automatic distribution of RTS firmware between the master and slave boards and ensuring version compatibility.

The invention discloses a self-checking method for a memory protection unit. The self-checking method comprises the following steps: setting an original first interrupt configuration table as a second interrupt configuration table which can only respond to self-checking abnormal interrupt and does not respond to other interrupts; remapping the interrupt entry address from the original interrupt vector table to a test interrupt vector table; and executing the test case to perform self-inspection on the memory protection unit. According to the self-checking method for the memory protection unit, the memory protection unit is subjected to self-checking, so that the memory access permission is effectively controlled by the memory protection unit, and the problem of latent faults caused by failure of the memory protection unit is avoided.

The application provides a method and system for interrupt fast response of embedded system code, and relates to the technical field of code interrupt response. The method comprises the following steps: configuring a first storage area and a second storage area, the response speed of the first storage area being less than the response speed of the second storage area; reading an original data storage block of the first storage area, and copying and writing data in the original data storage block of the first storage area into a copy data storage block of the second storage area; when a CPU kernel issues an interrupt access request, accessing an interrupt vector table copy from the copy data storage block of the second storage area through a VTOR register. The application can solve the technical problem of slow interrupt response speed in the prior art, further affecting the stability in a high real-time requirement environment, improve the interrupt response speed and the multi-interrupt request processing capacity, and thus improve the stability in the high real-time requirement environment.

The invention relates to a dual-region boot method based on a localized FT6713DSP. The method comprises the following steps: copying a designed and developed interrupt vector table vectors.sm, a boot startup boot.asm and a memory configuration cmd file into a work project to replace an original project file; annotating an IitEmif function in the initialization function of the DSP chip of the original project; the method comprises the steps that a DSP integrated development environment CCS is opened, a Texas Instruments Simulator is connected and configured in a simulator configuration file, and ram.bin and sd.bin are generated; the method comprises the following steps of: combining ram.bin and sd.bin into a file, and naming the file as ft67132in1. Bin; and a flash Burn project is used for programming the ft67132in1. Bin file into a FLASH chip which is started and guided by a DSP (Digital Signal Processor), so that compiling, programming and starting and guiding of engineering software are completed. According to the method, the software requiring high execution efficiency can run in the high-speed memory on the DSP chip, and the other software can run in the SDRAM external memory outside the chip, so that the software performance and the software function can be ensured, and a great expansion space can be reserved for software engineering.

The present invention relates to the field of virtual isolation technology, specifically providing a device isolation access method based on the ARM64 architecture virtualization mechanism, comprising the following steps: allocating a client virtual address and creating a first-stage address mapping page table; in response to a client accessing a device address space, generating a page fault, causing the processor to jump to an interrupt vector table for execution, and then to a data fault handler corresponding to the hypervisor for processing; entering a corresponding client page fault handler in the host operating system kernel based on the fault information to obtain a host physical address corresponding to the client physical address space; the corresponding client page fault handler in the host operating system kernel enters the hypervisor to transfer address space ownership; and creating a second-stage address mapping page table for the device address space. This solution solves the technical problem of a client being unable to achieve exclusive device access when using a virtual device.

The embodiment of the invention discloses an interrupt processing method and device, electronic equipment and a storage medium. According to the technical scheme provided by the embodiment of the invention, under the condition that the interrupt signal of the current task is detected, the interrupt vector table is obtained by accessing the rapid memory based on the independent bus, the function address is obtained based on the interrupt type of the interrupt signal, and the corresponding interrupt processing function is obtained based on the function address to serve as the target function; executing the register saving instruction, and saving the register content of the current task into an interrupt stack based on the register saving instruction; the target function is executed, after the target function is executed, the register loading instruction is executed, and the register content stored in the interrupt stack is recovered based on the register loading instruction. By the adoption of the technical means, the task recovery speed after interrupt processing can be increased, and the interrupt processing efficiency is improved.

This application discloses an interrupt reporting method and apparatus, and an interrupt configuration method and apparatus. The interrupt reporting method is applied to a node device that performs communication through a bus system, and the node device includes an interrupt vector table and an interrupt address table. The method includes: obtaining an interrupt event (S710); generating an interrupt message of the interrupt event, where the interrupt message includes an interrupt vector and an interrupt address, the interrupt vector is obtained from the interrupt vector table, and the interrupt address is obtained from the interrupt address table (S720); and sending the interrupt message to a network node through the bus system (S730).

This invention provides a method and terminal for writing information into MCU firmware. The method involves obtaining characteristic data of the MCU's interrupt vector table and determining the end address of the interrupt vector table based on the characteristic data. An array is created in the C language module of the original firmware, and the address of the array is mapped to the physical address of the assembly module in the original firmware. A linker script is obtained, and the address after the end address is defined as the physical address in the linker script. A parsing tool is created, which obtains the information space of the original firmware and writes customized information into the information space to generate new firmware. This application customizes and modifies information within the MCU firmware without changing the original firmware code. By utilizing the changing physical addresses within the firmware, it avoids third-party software arbitrarily tampering with firmware information through field matching and other methods, thus ensuring the security of the firmware information.

The embodiment of the invention discloses an address remapping method, a hardware online upgrading method, a circuit, a device and a system. Wherein the address remapping circuit is used for detecting whether a current instruction address of the microprocessor points to an interrupt vector table of an initial program code area, and when it is detected that the current instruction address of the microprocessor points to the interrupt vector table of the initial program code area, address offset is carried out on the current instruction address according to a target offset address; and reading the target reset vector in the code memory according to the shifted instruction address. Wherein the target offset address is an initial address of the target program code area. Therefore, the address remapping circuit is arranged to assist the microprocessor in performing program code area jumping, and the embodiment of the invention can enable the microprocessor to realize program code area jumping on the premise that the microprocessor does not have program code area jumping capability, thereby supporting deployment and operation of a multi-program code area storage architecture, and improving the program code area jumping efficiency. And thus, hardware online upgrading is supported.

The invention discloses a jump control method, device and equipment and a storage medium, the method is applied to embedded equipment, the embedded equipment comprises a bootstrap program area and an application program area, and the method comprises the following steps: after the bootstrap program area executes starting, reading a plurality of groups of flag bits in a nonvolatile memory; based on the multiple groups of flag bits, determining a target jump decision according to a preset priority rule; if the target jump decision indicates to jump to the application program area, performing integrity verification on a target code of the application program area; and after the verification is passed, dynamically redirecting the base address of the interrupt vector table to the initial address of the application program area, and skipping to the application program area from the bootstrap program area for execution. According to the method and the device, the target jump decision is determined based on the multiple groups of flag bits, the integrity check is performed before the application program area is jumped, and the base address of the interrupt vector table is dynamically redirected to the initial address of the application program area, so that compared with the prior art, the reliability and the safety of the jump process are improved.

The invention relates to the technical field of industrial equipment, and discloses an equipment monitoring system based on industrial edge computing, which comprises industrial equipment and data acquisition equipment connected with the industrial equipment, and is characterized in that the industrial equipment is used for configuring a target entry address for a target interrupt service program of which the vector number is a target vector number in an interrupt vector table through a BIOS (Basic Input / Output System); configuring a target vector number and an address of an interrupt controller of the industrial equipment for an interrupt trigger module of the data acquisition equipment; the data acquisition equipment is used for sending a data acquisition request to the interrupt controller of the industrial equipment; the industrial equipment is used for collecting operation data of the industrial equipment through a target interrupt service program and caching the operation data to a first buffer area of the industrial equipment; the data acquisition equipment is used for sending a data acquisition request to the industrial equipment; the industrial equipment is used for sending the operation data to the data acquisition equipment; the data acquisition device is used for receiving operation data. The operation data of the industrial equipment can be obtained without an operation system of the industrial equipment.

The invention relates to the technical field of virtual isolation, and particularly provides an equipment isolation access method based on an ARM64 architecture virtualization mechanism, which comprises the following steps of: distributing a virtual address of a client, and creating a first-stage address mapping page table; in response to the fact that the client accesses the device address space, a missing page data fault is generated, and the processor jumps to an interrupt vector table for execution and then jumps to a data fault processing program corresponding to the Hypervisor for processing; according to the fault information, entering a corresponding client page fault processing program in a host operating system kernel, and obtaining a host physical address corresponding to a client physical address space; a corresponding client page fault processing program in the kernel of the host machine operating system enters the Hypervisor to transfer the address space ownership; and creating a second-stage address mapping page table of the device address space. By means of the scheme, the technical problem that when the client uses the virtual device, the client cannot exclusively occupy device access is solved.

The application relates to an acquisition method and device of interrupt vector table data, electronic equipment and a storage medium. The method is applied to a memory control module in a system, the system comprising a memory, a central processing unit and the memory control module. The method comprises the following steps: receiving an address instruction sent by the central processing unit, the address instruction comprising a storage address of an interrupt vector table stored in the memory before a preset event occurs; in the case that the storage address belongs to a first storage area, acquiring an address offset between the first storage area and a second storage area, and updating the storage address according to the address offset to obtain a target storage address; and sending the target storage address to the memory to acquire interrupt vector table data stored by the interrupt vector table, and sending the interrupt vector table data to the central processing unit. Therefore, the rate and efficiency of the interrupt processing process are improved.

The invention discloses a fault positioning method and device for program exceptions, and the method comprises the steps: determining the fault type of the current program exception under the condition that an exception is detected in a program operation process; searching a fault processing function corresponding to the fault type from the interrupt vector table; obtaining program running information corresponding to the current moment based on the fault processing function; and locating the fault reason of the program exception according to the program operation information. According to the technical scheme provided by the embodiment of the invention, the accuracy of positioning the fault reason can be improved.