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15 results about "Interrupt vector table" patented technology
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An "interrupt vector table" (IVT) is a data structure that associates a list of interrupt handlers with a list of interrupt requests in a table of interrupt vectors. Each entry of the interrupt vector table, called an interrupt vector, is the address of an interrupt handler. While the concept is common across processor architectures, IVTs may be implemented in architecture-specific fashions. For example, a dispatch table is one method of implementing an interrupt vector table.
The invention discloses a self-checking method and device for a storage module, a chip, a medium and a product, and the method comprises the steps: obtaining a pre-established first interrupt vector table from a target storage module when a self-checking program is executed on an error-injected storage module and if a trigger instruction error correction error of the error-injected storage module is detected, the target storage module is not injected with errors; and executing an interrupt service program corresponding to the first interrupt vector table. Therefore, when an instruction error correction error occurs, the interrupt vector table is read from the non-error-injected storage module instead of being read from the error-injected memory, so that a CPU (Central Processing Unit) can be prevented from accessing an invalid interrupt vector table to enter a locking state, and a self-checking program can normally run.
The application discloses an online upgrading method of a multi-core microcontroller starting guide program, and the PC pointer is pointed to the RAM before erasing and writing the FLASH, and the B core is put to sleep and waits for the instruction; when the A core has an upgrading request, the B core receives the IPC interrupt request, the PC pointer jumps to the storage area of the interrupt vector table, the corresponding IPC interrupt service function address is searched, the corresponding upgrading service processing is executed, the PC pointer jumps back to the RAM after the execution is completed, the PC pointer is prevented from pointing to the invalid address, and thus the B core is prevented from abnormally stopping and the starting guide program upgrading operation is successfully completed.
This invention proposes a firmware update method for a controller with a master-slave board design, relating to the technical field of controller firmware updates. It adds a version identifier and version information to the end of the interrupt vector table in the firmwaresource code, which is simple, convenient, accurate, and universally applicable. It utilizes a large-capacity non-volatile memory on the motherboard and introduces a dual backup mechanism to prevent firmware update failures from causing the controller to be unable to run the RTS firmware. The host computer caches the firmware in the motherboard's non-volatile memory, and the slave board pulls the version from the motherboard's non-volatile memory, reducing the complexity of the firmware update process. For ease of management, an RTS package generator is used to package an RTS firmware package containing all RTS firmware for both the master and slave boards, and integrity verification information is added. The master and slave board bootloaders synchronize the RTS firmware version from the RTS firmware package cached in the non-volatile memory, achieving automatic distribution of RTS firmware between the master and slave boards and ensuring version compatibility.
The application provides a method and system for interrupt fast response of embedded system code, and relates to the technical field of code interrupt response. The method comprises the following steps: configuring a first storage area and a second storage area, the response speed of the first storage area being less than the response speed of the second storage area; reading an original data storage block of the first storage area, and copying and writing data in the original data storage block of the first storage area into a copy data storage block of the second storage area; when a CPU kernel issues an interrupt access request, accessing an interrupt vector table copy from the copy data storage block of the second storage area through a VTOR register. The application can solve the technical problem of slow interrupt response speed in the prior art, further affecting the stability in a high real-time requirement environment, improve the interrupt response speed and the multi-interrupt requestprocessing capacity, and thus improve the stability in the high real-time requirement environment.
The embodiment of the invention discloses an interrupt processing method and device, electronic equipment and a storage medium. According to the technical scheme provided by the embodiment of the invention, under the condition that the interrupt signal of the current task is detected, the interrupt vector table is obtained by accessing the rapid memory based on the independent bus, the function address is obtained based on the interrupt type of the interrupt signal, and the corresponding interrupt processing function is obtained based on the function address to serve as the target function; executing the register saving instruction, and saving the register content of the current task into an interrupt stack based on the register saving instruction; the target function is executed, after the target function is executed, the register loading instruction is executed, and the register content stored in the interrupt stack is recovered based on the register loading instruction. By the adoption of the technical means, the task recovery speed after interrupt processing can be increased, and the interrupt processing efficiency is improved.
This invention provides a method and terminal for writing information into MCU firmware. The method involves obtaining characteristic data of the MCU's interrupt vector table and determining the end address of the interrupt vector table based on the characteristic data. An array is created in the C language module of the original firmware, and the address of the array is mapped to the physical address of the assembly module in the original firmware. A linker script is obtained, and the address after the end address is defined as the physical address in the linker script. A parsing tool is created, which obtains the information space of the original firmware and writes customized information into the information space to generate new firmware. This application customizes and modifies information within the MCU firmware without changing the original firmware code. By utilizing the changing physical addresses within the firmware, it avoids third-party software arbitrarily tampering with firmware information through field matching and other methods, thus ensuring the security of the firmware information.
The embodiment of the invention discloses an address remapping method, a hardware online upgrading method, a circuit, a device and a system. Wherein the address remapping circuit is used for detecting whether a current instruction address of the microprocessor points to an interrupt vector table of an initial program code area, and when it is detected that the current instruction address of the microprocessor points to the interrupt vector table of the initial program code area, address offset is carried out on the current instruction address according to a target offset address; and reading the target reset vector in the code memory according to the shifted instruction address. Wherein the target offset address is an initial address of the target program code area. Therefore, the address remapping circuit is arranged to assist the microprocessor in performing program code area jumping, and the embodiment of the invention can enable the microprocessor to realize program code area jumping on the premise that the microprocessor does not have program code area jumping capability, thereby supporting deployment and operation of a multi-program code area storage architecture, and improving the program code area jumping efficiency. And thus, hardware online upgrading is supported.
The invention relates to the technical field of industrial equipment, and discloses an equipment monitoringsystem based on industrial edge computing, which comprises industrial equipment and data acquisition equipment connected with the industrial equipment, and is characterized in that the industrial equipment is used for configuring a target entry address for a target interrupt service program of which the vector number is a target vector number in an interrupt vector table through a BIOS (Basic Input / Output System); configuring a target vector number and an address of an interrupt controller of the industrial equipment for an interrupt trigger module of the data acquisition equipment; the data acquisition equipment is used for sending a data acquisition request to the interrupt controller of the industrial equipment; the industrial equipment is used for collecting operation data of the industrial equipment through a target interrupt service program and caching the operation data to a first buffer area of the industrial equipment; the data acquisition equipment is used for sending a data acquisition request to the industrial equipment; the industrial equipment is used for sending the operation data to the data acquisition equipment; the data acquisition device is used for receiving operation data. The operation data of the industrial equipment can be obtained without an operation system of the industrial equipment.