Interrupt-processing system for shortening interrupt latency in microprocessor

a technology of interrupt latency and interrupt processing, which is applied in the field of data processing system, can solve the problems of restricted interrupt service efficiency of the cpu, and achieve the effect of reducing interrupt latency and increasing interrupt service efficiency

Active Publication Date: 2005-03-17
NOVATEK MICROELECTRONICS CORP
View PDF4 Cites 30 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0014] The objective of the present invention is to provide a data processing system f

Problems solved by technology

Although this method is commonly used, the inter

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Interrupt-processing system for shortening interrupt latency in microprocessor
  • Interrupt-processing system for shortening interrupt latency in microprocessor
  • Interrupt-processing system for shortening interrupt latency in microprocessor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0029] Referring to FIG. 2, FIG. 2 is a function block diagram of a data processing system 2 according to the present invention. The data processing system 2 comprises a set of memory modules 30 for storing program instructions and data, a microprocessor 20, a power source 28 for providing electrical power to the data processing system 2, and a bus 60.

[0030] The set of memory modules 30 comprise a low-speed memory 32 and a high-speed memory 34. Both the low-speed memory 32 and the high-speed memory 34 store an interrupt vector table 36 individually for recording at least one entry instruction of an interrupt service routine 38. In this embodiment, there is one interrupt service routine 38. The entry instruction is the first instruction of the whole interrupt service routine 38.

[0031] The power source 28 comprises a switch 29. When the power source 28 is shut down, program instructions and data stored in the high-speed memory 34 are lost; however, program instructions and data stor...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention relates to a data processing system which comprises a memory module and a microprocessor. The memory modules comprise at least one low-speed memory and one high-speed memory; both store an interrupt vector table individually for recording the entry instruction of interrupt service routines. The microprocessor comprises a central processing unit (CPU) and a memory controller with a re-addressing device. Once an interruption occurs, the CPU generates and sends an interrupt vector address to the memory controller. If the vector is located in the range of interrupt vector table, the re-addressing device sends an enable signal to the high-speed memory to enable the CPU to fetch the entry instruction of interrupt service routines from the high-speed memory, not from the pre-determined low-speed memory. Hence, the interrupt latency is reduced.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a data processing system, and more particularly, the present invention relates to a data processing system for the interrupt latency of the microprocessor. [0003] 2. Description of the Prior Art [0004] In the microprocessor used in common electronic, non-personal computer, devices such as a digital camera, the interrupt vector table of the data processing system comprises a set of vector addresses; each address stores an entry instruction of the interrupt service routine (The entry instruction is the first instruction of the whole interrupt service routine). When the central processing unit (CPU) accepts an interrupt request, the CPU reads the interrupt vector table and executes the interrupt service routine corresponded to the interrupt request. [0005] In this type of data processing system, because the address of the reset vector is next to the other vectors, when booting the micro...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G06F9/26G06F13/24
CPCG06F13/24
Inventor YANG, PACHINCO
Owner NOVATEK MICROELECTRONICS CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap