Interrupt-processing system for shortening interrupt latency in microprocessor

Abstract

The invention relates to a data processing system which comprises a memory module and a microprocessor. The memory modules comprise at least one low-speed memory and one high-speed memory; both store an interrupt vector table individually for recording the entry instruction of interrupt service routines. The microprocessor comprises a central processing unit (CPU) and a memory controller with a re-addressing device. Once an interruption occurs, the CPU generates and sends an interrupt vector address to the memory controller. If the vector is located in the range of interrupt vector table, the re-addressing device sends an enable signal to the high-speed memory to enable the CPU to fetch the entry instruction of interrupt service routines from the high-speed memory, not from the pre-determined low-speed memory. Hence, the interrupt latency is reduced.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a data processing system, and more particularly, the present invention relates to a data processing system for the interrupt latency of the microprocessor. [0003] 2. Description of the Prior Art [0004] In the microprocessor used in common electronic, non-personal computer, devices such as a digital camera, the interrupt vector table of the data processing system comprises a set of vector addresses; each address stores an entry instruction of the interrupt service routine (The entry instruction is the first instruction of the whole interrupt service routine). When the central processing unit (CPU) accepts an interrupt request, the CPU reads the interrupt vector table and executes the interrupt service routine corresponded to the interrupt request. [0005] In this type of data processing system, because the address of the reset vector is next to the other vectors, when booting the micro...

AI Technical Summary

Benefits of technology

[0014] The objective of the present invention is to provide a data processing system for reducing the interrupt latency, so as to increase the interrupt service efficiency.

[0021] When the interruption occurs, the CPU generates an interrupt vector address to the memory controller. If the re-addressing device of the memory controller identifies that the address falls within the address range of the interrupt vector table, the re-addressing device sends out an enable signal to the high-speed memory which enables the CPU to fetch the corresponding entry instruction of the interrupt service routines in the high-speed memory, instead of the predetermined low-speed memory, so as to reduce the interrupt latency when fetching the program instruction.

[0022] The data processing system of the present invention, through the re-addressing device, allows the CPU to directly execute the interrupt service routine in the high-speed memory, thus not needing to fetch the entry instruction of the interrupt service routines in the low-speed memory. Therefore, the interrupt latency can be reduced.

Problems solved by technology

Although this method is commonly used, the interrupt service efficiency of the CPU is restricted.

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