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Low latency two-level interrupt controller interface to multi-threaded processor

A multi-threaded processor, waiting time technology, applied in the direction of electrical digital data processing, instruments, etc., can solve the problem of affecting the processing interrupt rate and so on

Active Publication Date: 2014-06-18
QUALCOMM INC
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  • Summary
  • Abstract
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  • Claims
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Problems solved by technology

The process associated with reading the AHB in order to retrieve the above information can add significant delay to interrupt latency, and thus further impact the rate at which interrupts are processed

Method used

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  • Low latency two-level interrupt controller interface to multi-threaded processor
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  • Low latency two-level interrupt controller interface to multi-threaded processor

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Embodiment Construction

[0020] Aspects of the invention are disclosed in the following description and associated drawings directed to specific embodiments of the invention. Alternative embodiments may be devised without departing from the scope of the present invention. Additionally, well-known elements of the invention will not be described in detail or will be omitted so as not to obscure the relevant details of the invention.

[0021] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term "embodiments of the invention" does not require that all embodiments of the invention include the discussed feature, advantage or mode of operation.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of the invention. ...

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Abstract

Systems and method for reducing interrupt latency time in a multi-threaded processor. A first interrupt controller is coupled to the multi-threaded processor. A second interrupt controller is configured to communicate a first interrupt and a first vector identifier to the first interrupt controller, wherein the first interrupt controller is configured to process the first interrupt and the first vector identifier and send the processed interrupt to a thread in the multi-threaded processor. Logic is configured to determine when the multi-threaded processor is ready to receive a second interrupt. A dedicated line is used to communicate an indication to the second interrupt controller that the multi-threaded processor is ready to receive the second interrupt.

Description

technical field [0001] The disclosed embodiments are directed to techniques for handling interrupts in a processor. More specifically, the exemplary embodiments are directed to systems and methods for reducing interrupt latency in a two-level interrupt controller configured for a multi-threaded processor. Background technique [0002] Processing systems typically support an interrupt mechanism in which an interrupt can asynchronously stop or suspend a processor's current thread of execution or instruction flow so that the interrupt can be serviced. Interrupts can be generated from various sources, including on-chip or off-chip external devices. Interrupts may also be generated internally within a processor or CPU, such as from one or more threads in a multi-threaded processor. [0003] To service an interrupt, a processor that receives the interrupt may execute an interrupt service routine (ISR). Each interrupt may include a specific ISR associated with that interrupt. B...

Claims

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Application Information

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IPC IPC(8): G06F13/24
CPCG06F13/24
Inventor 苏雷什·K·文库马汉提卢西恩·科德雷斯库埃里克·詹姆斯·普隆迪克陈旭峰培鑫·钟
Owner QUALCOMM INC
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