Apparatus and methods for speculative interrupt vector prefetching

Abstract

Techniques for interrupt processing are described. An exceptional condition is detected in one or more stages of an instruction pipeline in a processor. In response to the detected exceptional condition and prior to the processor accepting an interrupt in response to the detected exceptional condition, an instruction cache is checked for the presence of an instruction at a starting address of an interrupt handler. The instruction at the starting address of the interrupt vector table is prefetched from storage above the instruction cache when the instruction is not present in the instruction cache to load the instruction in the instruction cache, whereby the instruction is made available in the instruction cache by the time the processor accepts the interrupt in response to the detected exceptional condition.

Description

technical field [0001] The present disclosure relates generally to techniques for prefetching processor instructions, and in particular to speculative interrupt vector prefetching based on exception conditions. Background technique [0002] Many portable products such as cell phones, laptop computers, personal data assistants (PDAs) and the like utilize processors to execute programs such as communications and multimedia programs. Processing systems for these products include processor and memory complexes for storing instructions and data. Large-capacity main memory typically has a slow access time compared to the processor cycle time. Accordingly, memory complexes are conventionally organized into hierarchies based on the capacity and performance of cache memory, with the highest performance and lowest capacity cache memory located closest to the processor. Data and instruction caches may be separate or unified, or a combination of separate and unified. For example, a f...

AI Technical Summary

Problems solved by technology

The latency may be due in part to the fact that the interrupt handler is not resident in the instruction cache, resulting in long miss and fetch operations to retrieve instructions before the interrupt handler can execute , thereby reducing processor performance

One approach to reducing the latency involves locking an interrupt handler in the instruction cache, but this approach effectively reduces the size of the cache, which can further degrade processor performance

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