Interrupt processing method of multi-PCIE (Peripheral Component Interface Express) equipment system

Abstract

The invention discloses an interrupt processing method of a multi-PCIE (Peripheral Component Interface Express) equipment system, relating to the field of automatic control. In the invention, an interrupt register and an interrupt state register are arranged in advance, and the value of the interrupt state register changes along with the variation of a value of the interrupt register based on a preset rule; a notification message is sent when PCIE equipment generates interrupt, and an interrupt vector number and an interrupt register address which are configurated to the PCIE equipment in advance are carried in the message; after receiving the notification message, a main control end writes the interrupt vector number into the interrupt register corresponding to a mapping address; and an interrupt processing program which is registered in advance is called and executed based on the value of the interrupt state register, and the value of the interrupt state register is revised to restore an interrupt state of the PCIE equipment corresponding to the interrupt processing program into a non-interrupt state. The invention can process interrupt simultaneously generated by a plurality of PCIE equipments, and PCIE equipment which does not support an MSI (Medium-scale Integration) interrupt mode can apply the invention, therefore, the interrupt processing efficiency of the system is improved.

Description

technical field [0001] The invention relates to the field of automatic control, in particular to a multi-PCIE device system interrupt processing method. Background technique [0002] PCIE (Personal Computer Expansion Bus Interface) devices are a new generation of new architectures that can provide massive bandwidth and rich features to enable exciting new graphics applications. see figure 1 , which is a schematic diagram of the topology structure of a multi-PCIE device system, including a master control terminal and several PCIE devices as end points (End Point), wherein the master control terminal includes a CPU and a PCIE host bridge (PCIE host bridge), and the PCIE host bridge is mainly used for Realize the data conversion between the CPU bus data format supported by the CPU and the data format supported by each PCIE device. Usually, a PCIE Switch (switch) is also included to coordinate data exchange between multiple PCIE devices. [0003] Currently, in a system with mu...

AI Technical Summary

Problems solved by technology

[0006] In the process of implementing the present invention, the inventor finds that there are at least the following problems in the prior art: when multiple PCIE devices generate interrupts at the same time, multiple MSI messages will be generated, and after the PCIE main bridge receives multiple MSI messages, multiple MSI messages will be generated. The interrupt vector numbers are sequentially written into the interrupt registers pre-configured in the system. At this time, because the host control end has not had time to process the interrupt corresponding to the previous interrupt vector number, the latter interrupt vector number will overwrite the previous one in the interrupt register. An interrupt vector number, that is to say, for the host CPU that supports the MSI interrupt mode, it cannot handle the interrupts generated by multiple PCIE devices at the same time

Images