Flash memory device using semiconductor fin and method thereof

Abstract

A flash memory device according to the present invention includes a semiconductor fin including a top surface and a side surface originated from different crystal planes. The flash memory device comprises: insulating layers having different thicknesses formed on a side surface and a top surface of the semiconductor fin, a storage electrode, a gate insulating layer and a control gate electrode sequentially formed on the insulating layers. A thin insulating layer enables charges to be injected or emitted through it, and a thick insulating layer increases a coupling ratio. Accordingly, it is possible to increase an efficiency of a programming or an erase operation of a flash memory device.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 of Korean Patent Application 2004-69666 filed on Sep. 1, 2004, the entire contents of which are hereby incorporated by reference.BACKGROUND OF THE INVENTION[0002]The present invention relates to a semiconductor device and a method thereof, more particularly, to a semiconductor device using a semiconductor fin and a method thereof.[0003]For the past 30 years, silicon based integrated circuit devices, especially, metal oxide semiconductor MOS devices such as electric field effect transistors FET or MOSFET have been manufactured to have a high speed, a high integration or improved functions, decreasing a cost per a work process, so-called a throughput. However, as more highly integrated devices continue to be requested in view of high performance, high speed, low power consumption and costs, there occur various problems including deteriorating characteristics ...

AI Technical Summary

Benefits of technology

[0015]Exemplary embodiments of the present invention provide a flash memory device having a high scalability and a programming or erasing efficiency and a method thereof.

[0018]Therefore, electric charges are injected or emitted through the relatively thin insulating layer. In the meantime, due to the relatively thick insulating layer which can be formed on the top surface or the side surface of the semiconductor fin, a coupling ratio by a control gate is increased, thereby improving en efficiency of a programming or an erase operation.

[0019]In the meantime, in a case of a read operation for reading out information stored in the storage electrode, a speed of read operation is improved as channels are formed at both the side surface and the top surface of a semiconductor fin.

[0023]In one embodiment, if the top surface is {100} and the side surface is {110} plane, a thermal oxide layer is formed to have a relatively thicker thickness at the side surface than at the top surface. Therefore, electric charges are injected or emitted through the relatively thin thermal oxide layer at the top surface of the semiconductor fin. In the meantime, due to the relatively thick thermal oxide layer at the side surface, a coupling ratio by a control gate is increased, thereby improving an efficiency of a programming or an erase operation.

[0024]In the meantime, in a case of read operation for reading out information stored in the storage electrode, channels are formed at both of the side surface and the top surface of the semiconductor fin. Accordingly, efficiency of the read operation speed is improved.

[0028]In a case of a floating trap-type flash memory device, it is preferable that an insulating layer formed on the side surface is thinner than an insulating layer formed on the top surface of the semiconductor fin. For example, the side surface of the semiconductor fin represents a crystal plane {100}, and the top surface of the semiconductor fin represents a crystal plane {110}. Accordingly, charges are injected or emitted through a thin insulating layer on both side surfaces of the semiconductor fin, thereby performing a programming or an erase operation. In this case, as a thick insulating layer increasing a coupling ratio is formed on a top surface of a semiconductor fin, an efficiency of a programming or an erase operation may be degraded in comparison with a case of when the thick insulating layer is formed on a side surface of the semiconductor fin. As charges are injected or emitted through an insulating layer on both side surfaces of the semiconductor fin, a decrease of an efficiency of a programming or an erase operation may be compensated.

Problems solved by technology

However, as more highly integrated devices continue to be requested in view of high performance, high speed, low power consumption and costs, there occur various problems including deteriorating characteristics of a transistor.

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