16 results about "Acceptor impurity" patented technology

The invention discloses a gallium nitride electronic device and a preparation method thereof, and belongs to the technical field of semiconductors, the gallium nitride electronic device comprises a gallium nitride substrate and a semiconductor structure layer arranged on the gallium nitride substrate; the gallium nitride substrate is provided with shallow-energy-level donor impurities and deep-energy-level acceptor impurities, the deep-energy-level acceptor impurities are used for compensating the shallow-energy-level donor impurities, and the deep-energy-level acceptor impurities are metal impurities; a compensation layer is arranged at the interface of the gallium nitride substrate and the semiconductor structure layer, and the concentration of deep-energy-level acceptor impurities in the compensation layer is larger than that of the deep-energy-level acceptor impurities in the gallium nitride substrate. Metal impurities are doped in the gallium nitride substrate to serve as deep-energy-level acceptor impurities to compensate shallow-energy-level donor impurities, the concentration of impurity atoms adsorbed on the surface of the gallium nitride substrate can be reduced, and the performance of a gallium nitride electron tube device is improved.

A field effect transistor and a manufacturing method thereof, wherein the field effect transistor comprises: a source (13), a drain (14) and a gate (12); a channel region (11) is provided between the source (13) and the drain (14); an inner isolation layer (110) is provided between the gate (12) and the source (13) and between the gate (12) and the drain (14); the inner isolation layer (110) covers a portion of the channel region (11), wherein the inner isolation layer (110) includes donor impurities or acceptor impurities. The structure can reduce the on-resistance of the channel region (11) of the field effect transistor and maintain high carrier mobility in the channel region (11), thereby improving the performance of the field effect transistor.

The invention discloses a chlorosilane raw material purification system and method for reducing donor and acceptor impurities in polycrystalline silicon, and belongs to the technical field of polycrystalline silicon production, the chlorosilane raw material enters a first rectifying tower for primary rectification separation, the tower kettle of the first rectifying tower is extracted and flows into a silicon tetrachloride raw material tank, and the tower top of the first rectifying tower is extracted and flows into a second rectifying tower; tower top produced liquid of the first rectifying tower is subjected to secondary rectifying separation in a second rectifying tower, tower bottom produced liquid of the second rectifying tower flows into a third rectifying tower, and tower top produced liquid of the second rectifying tower flows into a mixer; tower kettle produced liquid of the second rectifying tower is subjected to third-time rectifying separation in a third rectifying tower, and tower top produced liquid of the third rectifying tower flows into a fourth rectifying assembly; the tower top produced liquid of the third rectifying tower is subjected to fourth rectifying separation in a fourth rectifying assembly, tower bottom produced liquid of the fourth rectifying assembly flows into a chlorosilane storage tank, and product liquid is produced from the tower top of the fourth rectifying assembly; and the tower kettle produced liquid of the third rectifying tower is subjected to adsorption and impurity removal in the first adsorber, and flows into a chlorosilane storage tank after impurity removal.

Ice is a new semiconductor material. Ice doping is accomplished by preparing aqueous solutions of acids (donor impurity) and aqueous solutions of bases (acceptor impurity) followed by freezing the solutions. A semiconductor device, namely a diode, is made by tightly joining or fusing a piece of acid-doped ice and a piece of base-doped ice.

The invention provides a semiconductor epitaxial structure and a preparation method and application thereof. A p-type semiconductor layer in the semiconductor epitaxial structure comprises a p-type barrier layer, the p-type barrier layer comprises at least one p-type structure, the p-type structure comprises a barrier front sub-layer, a p-type nitride microstructure and a barrier rear sub-layer which are arranged in sequence, and the p-type nitride microstructure comprises a plurality of nanometer protruding parts which are distributed on the surface, away from an active layer, of the barrier front sub-layer. The rear barrier sub-layer covers the plurality of nano convex parts and the surface, which is not covered by the nano convex parts, of the front barrier sub-layer; the material of the barrier front sub-layer is a first nitride doped with acceptor impurities, the material of the nanometer protruding part is a second nitride, and the valence band of the second nitride is higher than that of the first nitride. According to the invention, the p-type nitride microstructure is arranged in the p-type barrier layer so as to reduce the activation energy of acceptor doping, and a relatively strong polarization effect is formed at an interface, thereby cooperatively improving the hole concentration.

FIELD: microwave electronic devices.SUBSTANCE: in a low-noise microwave field-effect transistor on a semiconductor heterostructure, at least three quantum barrier layers of i-AlAs are additionally made, each with a thickness of 2-6 atomic monolayers, wherein each of said quantum barrier layers is located between the actual channel layer of InyGa1-yAs or a group of layers of the latter and the gate, wherein at least one quantum barrier layer is located between the doped layer and, or δ n-layer and the actual channel layer of InyGa1-yAs or a group of layers of the latter and at least one quantum barrier layer is located between the doped layer and, orδ n-layer and a gate, wherein the quantum barrier layers are separated from each other by at least one layer of narrow-band material AlxGa1-xAs, with a molar fraction of the chemical element Al x less than 0.4, with a thickness equal to or greater than 2 atomic monolayers, or a layer of GaAs, with a thickness equal to or greater than 2 atomic monolayers, between the actual channel layer InyGa1-yAs or a group of layers of the latter and the buffer layer, layers of GaAs, transition layers, quantum barrier layers i-AlAs, barrier layers, and layers doped with an acceptor impurity are made, on the last layer of the group of barrier layers, quantum barrier layers i-AlAs, barrier, transition and contact layers are made in a given sequence.EFFECT: increase in the gain factor and a reduction in the noise figure.1 cl, 1 dwg, 1 tbl

The invention discloses a gallium nitride semiconductor device and a preparation method thereof, and belongs to the technical field of semiconductors, and the preparation method comprises the steps: providing a gallium nitride substrate which is provided with shallow energy level donor impurities; a compensation layer and a semiconductor structure layer arranged on the compensation layer are formed on the surface of the gallium nitride substrate; wherein the compensation layer comprises a deep-energy-level acceptor impurity, the deep-energy-level acceptor impurity is used for compensating the shallow-energy-level donor impurity, and the deep-energy-level acceptor impurity is a metal impurity. By adopting the preparation method provided by the invention, the problems of serious electric leakage and small output power of the device caused by high concentration of impurity atoms adsorbed on the surface of the GaN substrate of the existing gallium nitride semiconductor device can be solved, and the performance of the gallium nitride semiconductor device can be improved.

The present invention discloses a semiconductor device terminal structure and its manufacturing process. The semiconductor device terminal structure is disposed in an N-P-N-type doped wide-bandgap semiconductor epitaxial wafer. This structure uses ion implantation or epitaxy plus ion implantation to provide an N-type doped electric field cutoff region and an N-type doped charge compensation region in a P-type doped buried layer. The deepest portion of the N-type doped electric field cutoff region exceeds the P-type doped buried layer and extends into the N-type doped drift region. This structure can achieve a gradual decrease in the equivalent acceptor impurity atomic weight of the P-type doped buried layer from the main junction region to the terminal region and from the cutting path region to the terminal region by adjusting the spacing and volume of at least one N-type doped charge compensation region and doping. This ultimately reduces the curvature effect of the main junction region, alleviates the problem of electric field concentration near the main junction, and avoids premature breakdown of the main junction of the power device.

To provide a nitride semiconductor device capable of reducing fluctuations in a threshold voltage.SOLUTION: A nitride semiconductor device 10 includes: an electron transit layer; an electron supply layer 42 located on the electron transit layer and having a band gap larger than that of the electron transit layer; a source electrode 28 and a drain electrode 30 in contact with an electron supply layer 42, a gate layer 46 including a bottom surface in contact with the electron supply layer 42 and located between a source electrode 28 and the drain electrode 30 and containing an acceptor impurity; and a gate electrode 26 located on the gate layer 46. The gate layer 46 includes a first contact surface 46A1 and a second contact surface 46A2 in contact with the gate electrode 26. The gate layer 46 is configured such that a gate current per unit area flowing through a second contact surface 46A2 is larger than a gate current per unit area flowing through the first contact surface 46A1 when a gate voltage is applied to the gate electrode 26.SELECTED DRAWING: Figure 2

The N-type crystalline silicon back contact battery comprises a silicon wafer substrate, a phosphorus-doped SiOx layer, a SiOx mask layer and a SiNx anti-reflection layer are sequentially arranged on the front face of the silicon wafer substrate from inside to outside, the back face of the silicon wafer substrate is divided into positive electrode areas and negative electrode areas which are alternately arranged, and height compensation areas are arranged on the two sides, close to the negative electrode areas, of the positive electrode areas. By doping a proper amount of boron atoms on the surface layer of the N-type silicon wafer substrate between the P region and the N + region, when the concentration of acceptor impurity boron atoms is close to the concentration of donor impurity phosphorus atoms, a height compensation region is formed, the concentrations of free electrons and free holes in the height compensation region are very low, and the mobility is reduced due to scattering of more impurities, so that the performance of the device is improved. Therefore, the resistivity can be sharply increased, the channel resistance is further increased, the distance between the P region and the N + region can be conveniently reduced, and the battery efficiency is improved. In addition, the distance between the P region and the N + region is reduced, so that over-high leakage current does not need to be worried.

This invention discloses a method for increasing the hole concentration in p-type group III nitride materials and its application. The method includes: during and / or after the growth of the p-type group III nitride material, reacting the p-type group III nitride material with halogen-based active atoms and / or halogen-based active groups to remove some group III atoms from the p-type group III nitride material, thereby generating cation vacancies in the p-type group III nitride material; and activating acceptor impurities in the p-type group III nitride material containing the cation vacancies. This invention provides a method for increasing the hole concentration in AlGaN semiconductor materials, overcoming the limitations of traditional p-type AlGaN materials such as low acceptor Mg atom incorporation efficiency and severe self-compensation effects. It can utilize group III cation vacancies to significantly increase the concentration of Mg acceptor impurities at group III atom lattice sites, thereby significantly increasing the hole concentration in the p-type AlGaN material.

The invention provides a semiconductor device and a manufacturing method thereof, and the semiconductor device comprises a gallium oxide substrate which comprises a first surface and a second surface which are oppositely disposed; the gallium oxide epitaxial layer covers the first surface of the gallium oxide substrate; the high-resistance doped gallium oxide layer is located on the gallium oxide epitaxial layer; the groove extends inwards from the surface of the high-resistance type doped gallium oxide layer by a certain depth, the high-resistance type doped gallium oxide layer comprises a first high-resistance region and a second high-resistance region, the first high-resistance region surrounds the bottom and part of the side wall of the groove, the second high-resistance region is located on the outer side of the side wall of the groove, and the first high-resistance region and the second high-resistance region are arranged in parallel. The doping concentration of the P-type acceptor impurity in the second high-resistance region is higher than that of the P-type acceptor impurity in the first high-resistance region; the source electrode metal layer is located on the second high-resistance region; the gate dielectric layer covers the side wall and the bottom of the groove in a conformal manner; the gate metal layer covers part of the surface of the gate dielectric layer; and the drain metal layer covers the second surface of the gallium oxide substrate.

The invention discloses an HEMT (High Electron Mobility Transistor) device epitaxial structure based on a GaN material and an application of the HEMT device epitaxial structure. A first buffer layer formed on the substrate; a stack layer formed on the first buffer layer; the channel layer is formed on the laminated layer; a barrier layer formed on the channel layer; wherein the lamination comprises a plurality of lamination units which are sequentially laminated along the direction deviating from the substrate, each lamination unit comprises an AlGaN sub-layer close to the first buffer layer, a first lattice layer which is arranged on the AlGaN sub-layer and comprises GaN, and a second lattice layer which is arranged on the first lattice layer and comprises GaN, the first lattice layer is a doped lattice layer, and the second lattice layer is a doped lattice layer. The second lattice layer is an undoped lattice layer. By adopting the AlGaN / GaN composite structure and doping the acceptor impurities at intervals, the GaN crystal quality can be improved, and the HEMT device performance is enhanced.

A P-type gallium oxide and a preparation method for a P-type gallium oxide. The preparation method for a P-type gallium oxide comprises: providing a substrate, the material of which comprises β-gallium oxide; and co-doping the substrate with a shallow-level acceptor impurity and a deep-level acceptor impurity, wherein the shallow-level acceptor impurity and oxygen are congeners. During co-doping with the deep-level acceptor impurity and the shallow-level acceptor impurity, a deep-level acceptor of the deep-level acceptor impurity can work in conjunction with the acceptor level of the shallow-level acceptor impurity to further shift the Fermi level upward toward the valence band maximum, and the combination effect substantially improves the stability of the P-type electrical conductivity of the β-gallium oxide.

This application provides a fabrication process and semiconductor device for an ESD protection device. The process includes: providing a semiconductor substrate; performing a first ion implantation of the semiconductor substrate with a first conductivity type, implanting a first dose of a first impurity; performing a second ion implantation of the semiconductor substrate with a second conductivity type, implanting a second dose of a second impurity, the second impurity being a donor impurity or acceptor impurity opposite to the first impurity, the difference between the second dose and the first dose being configured to be equivalent to the net doping dose of the target dose implantation within a preset range; and annealing the semiconductor substrate after the two ion implantations to activate the implanted impurities. This application achieves low-concentration doping by controlling the difference between the two higher dose implantations, solving the problems of insufficient process window and poor equipment stability in low-dose implantation, improving process stability and device performance consistency, and reducing production costs.

The application provides a semiconductor epitaxial structure, a preparation method and application thereof. The p-type semiconductor layer of the semiconductor epitaxial structure comprises a p-type barrier layer, the p-type barrier layer comprises at least one p-type structure, the p-type structure comprises a barrier front sublayer, a p-type nitride microstructure and a barrier rear sublayer arranged in sequence, the p-type nitride microstructure comprises a plurality of nano protrusions distributed on the surface of the barrier front sublayer away from the active layer, the barrier rear sublayer covers the plurality of nano protrusions and the surface of the barrier front sublayer not covered by the nano protrusions; the material of the barrier front sublayer is a first nitride doped with an acceptor impurity, the material of the nano protrusions is a second nitride, and the valence band of the second nitride is higher than that of the first nitride. The p-type nitride microstructure is arranged in the p-type barrier layer to reduce the activation energy of the acceptor doping, and a stronger polarization effect is formed at the interface, so that the hole concentration is improved.