14 results about "Acceptor doping" patented technology

The invention provides a semiconductor epitaxial structure and a preparation method and application thereof. A p-type semiconductor layer in the semiconductor epitaxial structure comprises a p-type barrier layer, the p-type barrier layer comprises at least one p-type structure, the p-type structure comprises a barrier front sub-layer, a p-type nitride microstructure and a barrier rear sub-layer which are arranged in sequence, and the p-type nitride microstructure comprises a plurality of nanometer protruding parts which are distributed on the surface, away from an active layer, of the barrier front sub-layer. The rear barrier sub-layer covers the plurality of nano convex parts and the surface, which is not covered by the nano convex parts, of the front barrier sub-layer; the material of the barrier front sub-layer is a first nitride doped with acceptor impurities, the material of the nanometer protruding part is a second nitride, and the valence band of the second nitride is higher than that of the first nitride. According to the invention, the p-type nitride microstructure is arranged in the p-type barrier layer so as to reduce the activation energy of acceptor doping, and a relatively strong polarization effect is formed at an interface, thereby cooperatively improving the hole concentration.

The invention relates to a heat-sensitive material with a high lift-to-drag ratio and a preparation method thereof, and belongs to the technical field of preparation of electronic ceramic elements. The preparation method comprises the following steps: mixing nano barium titanate powder and donor-doped barium titanate powder, molding, and sintering to obtain the barium titanate-based thermal sensitive ceramic, the nano barium titanate powder is acceptor doped nano barium titanate powder or undoped nano barium titanate powder; the sintering is carried out under the condition of 1000 to 1500 DEG C for 0.5 to 10 hours. According to the invention, high density and low room temperature resistance are realized, effective oxidation of ceramic grain boundaries can be realized, acceptor doping is realized at the grain boundaries, and the thermal sensitive ceramic has obviously improved thermal sensitive performance. The two-step sintering method preferably adopted by the invention can effectively improve the density of the sintered ceramic and reduce the grain size, is beneficial to improving the performance stability of the thermal sensitive ceramic, and is beneficial to miniaturization of a thermistor with a multi-layer chip structure.

A method of manufacturing a photodetector device, comprising the steps of: fabricating a cadmium-rich structured coating (122) on a substrate (110) of Cd x Hg 1‑x Te, and using a first etch mask; performing an etch to enlarge the via of the first etch mask or to enlarge the via of an intermediate layer etched with the structured coating, thereby forming a second etch mask; implanting an acceptor dopant element into the substrate (110) through the second etch mask (150), and activating and diffusing the acceptor dopant element to form at least one P-doped region in the semiconductor substrate; performing a selective interdiffusion anneal of cadmium, thereby forming a cadmium-rich concentration well with a lateral gradient of cadmium concentration in each P-doped region; and fabricating at least one electrical contact pad (171) at each via (121) in the structured coating (122).

A method for manufacturing a photodetection device, which includes the following steps:making a cadmium-rich structured coating, over a substrate of CdxHg1-xTe, and using a first etching mask; etching to enlarge the through openings of the first etching mask or the through openings of an interlayer etched with the structured coating, so as to form a second etching mask; injecting acceptor doping elements into the substrate, throughout the second etching mask, and activating and diffusing the acceptor doping elements to form at least one P doped region in the semiconductor substrate; selective interdiffusion annealing of cadmium, so as to form in each P doped region a cadmium-rich concentrated well with a cadmium concentration lateral gradient; and making at least one electrical contact pad, at each through opening in the structured coating.

The application discloses an epitaxial structure of a semiconductor device, a preparation method of the epitaxial structure and the semiconductor device. The epitaxial structure of the semiconductor device comprises a substrate and an epitaxial layer located on one side of the substrate. The epitaxial layer comprises at least one back barrier layer. The back barrier layer comprises AlGaN and acceptor doping ions. The acceptor doping ions are used to form acceptor energy levels in the back barrier layer. According to the application, the acceptor energy levels are formed by introducing the acceptor doping ions into the AlGaN back barrier layer, the electrons in the back barrier layer are captured, the current collapse phenomenon is effectively relieved, the leakage current is reduced, and therefore the crystal quality and the device reliability are improved.

The invention relates to a low-impact-flow ceramic PTC (Positive Temperature Coefficient) material and a preparation process thereof, and belongs to the technical field of ceramic PTC materials. On one hand, the pinning effect is formed and the NTC effect is reduced through heavy donor and heavy acceptor doping, so that the impulse flow is reduced, and on the other hand, excessive silicon oxide is introduced to adsorb impurities and reduce the NTC effect, so that the impulse flow is reduced. According to the invention, the impulse current can be reduced on the premise of not changing the starting current, and the application prospect is excellent.

The application relates to a low-impact ceramic PTC material and a preparation process thereof, and belongs to the technical field of ceramic PTC materials. In the application, heavy donor heavy acceptor doping is adopted to form pinning effect, reduce NTC effect, and thus reduce impact flow; on the other hand, excess silicon oxide is introduced to absorb impurities, reduce NTC effect, and thus reduce impact flow. The application can reduce impact flow without changing starting current, and has excellent application prospect.

This invention discloses an enhanced high electron mobility transistor (HEMT) power device and its fabrication method. The device comprises, from bottom to top, a substrate, a pre-lay layer, a nucleation layer, a gradient layer, a high-resistivity layer, a channel layer, a barrier layer, and a P-type layer. A source and drain are formed on the barrier layer, and a gate is formed on the P-type layer. Passivation layers are disposed on the barrier layers between the source and the P-type layer, and between the drain and the P-type layer, respectively. The P-type layer comprises an InGaN superlattice and an AlGaN superlattice stacked on top of the InGaN superlattice. This invention can simultaneously achieve multiple process objectives, including improving material crystal quality, increasing hole injection efficiency, and enhancing device saturation current, threshold voltage, and reliability. It effectively improves the activation efficiency of acceptor doping and increases the hole carrier concentration of the P-type layer material. Correspondingly, it can also reduce the acceptor doping concentration and decrease the impurity scattering mechanism affecting hole carriers.

This invention belongs to the field of semiconductors and relates to a method for fabricating enhancement-mode gallium oxide transistors based on nitrogen ion channel implantation doping. An n-type β-Ga₂O₃ epitaxial layer is fabricated on the gallium oxide transistor substrate. High-concentration n-type implantation is then performed on the source and drain electrode sites on the epitaxial layer, followed by annealing activation. Subsequently, source and drain electrodes are fabricated to form ohmic contacts. Next, the gate termination positions of the channel region are defined by photolithography, and nitrogen ions are implanted into the gate termination positions to form nitrogen acceptor doped regions. After implantation, rapid annealing activates the nitrogen acceptor doped regions and repairs lattice damage. An insulating layer is then deposited in a portion of the epitaxial layer, and the gate electrode is fabricated, ultimately obtaining the desired gallium oxide transistor. This invention utilizes nitrogen ions to form acceptor doping in the channel region, achieving enhancement-mode operation by compensating for n-type charge carriers, effectively eliminating defects such as sidewall lattice damage, increased interface state density, and electric field concentration at channel corners caused by etching processes.

Power transistor (100) with an adapted threshold voltage and with a structure which has fins (102) and trenches alternating on an n-epitaxial layer (101), wherein the fins (102) have channel regions (106) and the trenches comprise trench bottoms and trench side surfaces, wherein first gate oxide regions (104a) of a gate oxide (104) are arranged on the trench bottoms and second gate oxide regions (104b) of the gate oxide (104) are arranged on the trench side surfaces, wherein gate electrodes (103) are arranged on the first gate oxide regions (104a) of the gate oxide (104), wherein regions (105) with an acceptor-like doping for adapting the threshold voltage are arranged laterally of the fins (102) between the second gate oxide regions (104b) of the gate oxide (104) and the channel regions (106) of the fins (102). (Vth) of the power transistor (100).

This invention belongs to the field of silicon carbide semiconductor material preparation technology. It discloses a method and system for producing P-type silicon carbide using a low-energy-consumption, high-consistency liquefaction method. This method overcomes the limitations of existing liquefaction methods, which focus on extensive parameter control and single-stage optimization. It constructs a fully process-driven preparation system by dynamically adapting acceptor doping, coordinating liquefaction reaction energy consumption, and controlling crystal growth consistency. Through modeling and precise solving, it addresses specific challenges in existing technologies such as poor acceptor doping adaptability, high liquefaction reaction energy consumption, and insufficient crystal growth consistency. This achieves low-energy consumption, high consistency, and high purity in the preparation of P-type silicon carbide, significantly improving the product's electrical performance and mass production adaptability. It provides a new technological path for the industrial-scale, low-cost, high-quality production of P-type silicon carbide.

The application discloses an electromagnetic voltage transformer current-limiting and resonance-eliminating device based on PTC characteristics and an optimization method thereof, and relates to the technical field of power protection. The device comprises the following steps: adopting donor doping, acceptor doping and glass phase modification to regulate and control barium titanate-based positive temperature coefficient ceramics to form a positive temperature coefficient core; forming a conductive electrode layer on the positive temperature coefficient core; connecting the positive temperature coefficient core in series according to the number of multiple pieces and in series according to the insulation packaging parameters, and then connecting the positive temperature coefficient core in series between a primary neutral point of a voltage transformer and the ground to form a current-limiting and resonance-eliminating device; and arranging the collected zero sequence voltage and neutral point current according to a unified sampling time mark to form a joint discrimination signal. The application can improve the identification accuracy among frequency resonance, fundamental frequency ferromagnetic resonance, arc grounding and single-phase grounding by first screening abnormal states in layers and then further distinguishing power frequency dominant abnormalities, so that the misjudgment and misoperation are reduced.

The invention discloses a boundary condition processing method and device applied to semiconductor device simulation. The method comprises the following steps: carrying out iterative calculation on a metal half boundary condition by utilizing acquired ionization donor doping concentration and ionization acceptor doping concentration; in the current iteration process, dynamically adjusting the metal half boundary condition of the current iteration process by using a solving result obtained in the previous iteration process; after the metal half boundary condition of the current iteration process is substituted into the nonlinear simulation equation set, a solving result of the current iteration process is obtained, and iteration is terminated when it is determined that the solving result of the current iteration process converges or the number of iterations reaches the preset number of iterations. According to the method, the convergence and the accuracy of semiconductor device simulation are improved by dynamically adjusting the boundary condition.

The application provides a semiconductor epitaxial structure, a preparation method and application thereof. The p-type semiconductor layer of the semiconductor epitaxial structure comprises a p-type barrier layer, the p-type barrier layer comprises at least one p-type structure, the p-type structure comprises a barrier front sublayer, a p-type nitride microstructure and a barrier rear sublayer arranged in sequence, the p-type nitride microstructure comprises a plurality of nano protrusions distributed on the surface of the barrier front sublayer away from the active layer, the barrier rear sublayer covers the plurality of nano protrusions and the surface of the barrier front sublayer not covered by the nano protrusions; the material of the barrier front sublayer is a first nitride doped with an acceptor impurity, the material of the nano protrusions is a second nitride, and the valence band of the second nitride is higher than that of the first nitride. The p-type nitride microstructure is arranged in the p-type barrier layer to reduce the activation energy of the acceptor doping, and a stronger polarization effect is formed at the interface, so that the hole concentration is improved.