Method for preparing FinFET on germanium and III-V semiconductor material substrate

Abstract

The invention discloses a method for preparing FinFET on a germanium and III-V semiconductor material substrate, and the method mainly comprises following steps of forming a source drain and a slender graphic structure which is connected to the source drain; forming an oxidization isolation layer; forming a grid structure and a source drain structure; and forming metal contact and metal interconnection. Due to the adoption of the method, the FinFET is easily formed on the germanium and III-V semiconductor material substrate, the entire process flow is completed on the germanium and III-V semiconductor material substrate and is completely similar to the manufacturing technology of a conventional ultra-large-sized integrated structure, and the preparation process has characteristics of simpleness, convenience and short period. In addition, the minimal width of the FinFET prepared by the method can be controlled within 20 nanometers, and a multi-grid structure can provide good grid control capacity and is very suitable for preparing ultra-short-channel devices to further reduce the size of the devices. The FinFET prepared by the method has low power consumption.

Description

technical field [0001] The invention provides a method for preparing a FinFET on a germanium and III-V semiconductor material substrate, and belongs to the technical field of VLSI manufacturing. Background technique [0002] Today's semiconductor manufacturing industry is developing rapidly under the guidance of Moore's Law, continuously improving the performance and integration density of integrated circuits, while reducing the power consumption of integrated circuits as much as possible. Therefore, the preparation of ultra-short trench devices with high performance and low power consumption will become the focus of the future semiconductor manufacturing industry. After entering the 22nm technology node, the leakage current of traditional planar field effect transistors continues to increase, as well as the increasingly serious short channel effect and leakage-induced barrier lowering (DIBL) effect, which cannot be well adapted to the development of semiconductor manufactur...

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Problems solved by technology

But its disadvantages are: (1) The process cost is too high, and the SOI substrate is quite expensive; (2) The source-drain lifting technology is required, otherwise the extended resistance of the source and drain is too large, resulting in too small on-state current and poor device performance; (3) There is no body extraction, so the threshold voltage cannot be adjusted through the substrate bias effect

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