73results about How to "Increased avalanche tolerance" patented technology

The invention relates to a soft fast recovery diode and a manufacturing method thereof. The diode comprises an N type intrinsic region, a back N<+> buffer region, an anode metal layer and a cathode metal layer, wherein the back N<+> buffer region is formed on the back face of the N type intrinsic region; a P type emitting region is formed between the front face of the N type intrinsic region and the anode metal layer; mask oxide layers are formed symmetrically at the two ends of the anode metal layer; a P type high-resistance region is formed on the boundary of an active region; a P<+> ohmic contact layer is formed in the center of the active region; an overall lifetime control region is formed on the entire diode, and covers all structural layers of the diode; a localized lifetime control layer is positioned close to the P<+> ohmic contact layer in the P type emitting region along the axial direction of the diode; the localized lifetime control layer is positioned in a plane constructed by the P type emitting region and the P type high-resistance region along a direction which is vertical to the axial direction of the diode. The soft fast recovery characteristic of a device is realized by adopting an overall-localized lifetime control way; by arranging the high-resistance region, the snow slide resistance of the device is improved.

The invention provides a novel silicon carbide junction barrier Schottky diode. The novel silicon carbide junction barrier Schottky diode comprises a first conductive type of silicon carbide substrateand a first conductive type of silicon carbide epitaxial layer which are arranged in a lamination way, wherein an active region, a protection ring and a second conductive type of terminal field limitation ring are sequentially arranged on an upper surface of the first conductive type of silicon carbide epitaxial layer from center to outside, the active region comprises a plurality of second conductive types of junction barrier regions which are arranged at intervals, the distance between adjacent second conductive types of junction barrier regions is gradually increased along a direction fromthe protection ring to the center of the active region, and the widths of the second conductive types of junction barrier regions are gradually reduced. The invention also provides a fabrication method of the silicon carbide junction barrier Schottky diode.

The invention discloses an IGBT device and a preparation method thereof, relates to a power semiconductor device, and provides a device structure design scheme capable of improving avalanche tolerance on the basis of not lowering other performance indexes (such as forward conduction voltage drop V<on>, switching speed, load short-circuit capacity and the like) of the IGBT. The invention provides a novel IGBT device structure and a preparation method thereof. Beneficial effects are achieved as follows: compared with the IGBT device in the prior art, the IGBT device disclosed by the invention can realize more stable breakdown characteristic, so that the avalanche tolerance of the device can be greatly improved, thereby enabling the device to the safer and more reliable in an actual high-speed high-power application.

The invention relates to a trench gate super-junction MOSFET device and a preparation method therefor. The device comprises a semiconductor substrate and a cellular region positioned in the central region of the semiconductor substrate; the semiconductor substrate comprises a first conductive type substrate and a first conductive type epitaxial layer positioned above the first conductive type substrate; a super-junction structure is arranged in the first conductive type epitaxial layer in the cellular region; second conductive type columns and the first conductive type epitaxial layer can formthe super-junction structure; a cellular trench is formed between the adjacent second conductive type columns; an insulating oxide layer and conductive polysilicon are arranged in each cellular trench; by virtue of the super-junction structure and the trench gate structure, on resistance can be lowered effectively; the first conductive type epitaxial layer outside the cellular trench opening is covered with the insulating oxide layer; the insulating oxide layer outside the cellular trench opening is covered with the conductive polysilicon at the same time; and by virtue of the insulating oxide layer outside the cellular trench opening and the conductive polysilicon, avalanche resistance can be improved, and compact structure and safety and reliability are realized.

The invention belongs to the technical field of manufacturing of semiconductor devices and relates to a high-snow-slide-tolerance deep-groove power device. The device comprises a first electric-condition-type silicon substrate and a first electric-condition-type silicon epitaxial layer, grooves are formed in the first electric-condition-type silicon epitaxial layer, and field oxygen layers, shieldgrids, grid electrodes and grid oxygen layers are arranged in the grooves; second electric-condition-type body areas and first electric-condition-type source areas are arranged between the adjacent grooves, and insulation dielectric layers and source electrode metal are arranged in the grooves and the first electric-condition-type source areas. The device is characterized in that in a platform area between the adjacent grooves, the source electrode metal is in contact with the second electric-condition-type body areas through two through holes, and second electric-condition-type source areasare arranged below all the through holes; a traditional single through hole is improved into double through holes, current can be effectively inhibited from being gathered to the center of a platform,the generation of weak point breakdown is inhibited accordingly, the epitaxial layer with lower specific resistance and the thicker field oxygen layers can be adopted for the deep-groove device, andthen the conduction resistance of the device is lowered.

The invention relates to a method for manufacturing a super-junction high-voltage power device. The method comprises the following steps of: providing an n-type heavy doping n+ substrate, forming an n-type epitaxial layer on the n+ substrate, and forming a p well region and a composite buffer layer; growing a field oxide layer on a silicon chip, defining an active region of the device, growing a gate oxide layer, and defining an area etched by polycrystalline silicon at the first time; performing deep p+ implantation on the surface of the whole semiconductor silicon chip, wherein a p+ area can be defined in a polycrystalline silicon area formed by the previous process; putting the silicon chip in polycrystalline silicon etching solution, performing secondary etching on the polycrystalline silicon by controlling the etching time and the etching rate, and forming an n-type source region n+; depositing a dielectric layer on the surface of the whole semiconductor silicon chip, defining a contact hole area, and etching the oxide layer; and depositing a metal layer, defining an etching area through photoetching, and performing metal etching. By the method, the avalanche tolerance of the device is improved, the reliability of the device is improved, and the threshold voltage and on-resistance of the device are not influenced.

The invention discloses a power semiconductor device, which comprises a cell area, a terminal protection area, a first type of insulating dielectric body and a first type of electric conductor, wherein the cell area comprises a substrate of a first conductivity type and an epitaxial layer of a first conductivity type; a U-shaped groove is formed in the epitaxial layer of the first conductivity type; the groove is filled with the first type of insulating dielectric body and the first type of electric conductor; the first type of insulating dielectric body is arranged in a manner of surroundingthe first type of electric conductor; inner grooves are formed between one of two sides of the upper end of the first type of electric conductor and the first type of insulating dielectric body and between the other side and the epitaxial layer of the first conductivity type separately, and the cross section of each inner groove is in a right-angled trapezoid form; an acute angle in a right-angledtrapezoid form is formed between the first type of insulating dielectric body and the first type of electric conductor; and gate-conductive polysilicon matched with the inner grooves is arranged in the inner grooves. The invention further discloses a manufacturing method of the power semiconductor device. According to the power semiconductor device, the on-resistance of the device is obviously reduced.

The invention provides a groove type field effect transistor structure and a preparation method thereof. The preparation method comprises the steps: providing a substrate, forming an epitaxial layer, forming a device groove in the epitaxial layer, and forming a shielding dielectric layer, a shielding gate layer, a first isolation dielectric layer, a gate dielectric layer, a gate layer, a second isolation dielectric layer, a body region, a source electrode, a source electrode contact hole, a source electrode structure and a drain electrode structure. In the preparation process of the groove type field effect transistor structure, a self-alignment process is adopted, so that the pitch of a cell unit is not limited by the exposure capability of a photoetching machine and the alignment precision of the photoetching machine, the pitch of the cell unit of a device can be further reduced, the cell density is improved, the channel resistance of the device is reduced, and a device structure with stable electrical parameters and low characteristic on-resistance is obtained; by arranging a T-shaped source electrode structure, the contact area between a source electrode structure and a source and the contact area between the source electrode structure and the body region are increased, so that the contact resistance of the source can be effectively reduced, and the avalanche tolerance of the device is improved.

The invention provides a high-avalanche capability power semiconductor transistor structure, which comprises an N-type substrate used as a drain region, wherein an N-type epitaxial layer is arranged on the N-type substrate; P-type strip body regions are arranged on the surface of the N-type epitaxial layer; a heavily doped N-type source region and a heavily doped P-type source region are arranged on the surface of each P-type strip body region; an insulated gate oxidation layer is arranged on the N-type epitaxial layer; conductive polysilicon is arranged on the insulated gate oxidation layer, and is located at the upper part of the region between the adjacent P-type strip body regions and two sides of the conductive polysilicon respectively cover the adjacent P-type strip body regions; an insulated medium layer is arranged on the conductive polysilicon; the heavily doped N-type source regions and the heavily doped N-type source regions are connected with a source metal; the high-avalanche capability power semiconductor transistor structure is characterized in that the P-type strip body regions extend towards the N-type epitaxial layer to form a plurality of P-type arched body regions; and the P-type arched body regions are evenly distributed on the P-type strip body regions and are embedded into the N-type epitaxial layer. According to the high-avalanche capability power semiconductor transistor structure, a preparation method of a traditional power semiconductor transistor is reserved; the avalanche capability is improved; the chip area is reduced; and the cost is relatively low.

The invention discloses a Schottky diode and a preparation method thereof. The Schottky diode comprises a semiconductor substrate layer; a drift layer is located on the semiconductor substrate layer and comprises a first drift region and a second drift region, the second drift region is located on the side, opposite to the semiconductor substrate layer, of the first drift region, and the doping concentration of the second drift region is larger than that of the first drift region; an auxiliary doping layer is located in a part of the second drift region, and the conduction type of the auxiliary doping layer is opposite to that of the drift layer; a number of main doping layers are located in the drift layer and distributed around the auxiliary doping layer at intervals, and the conduction type of the main doping layers is the same as that of the auxiliary doping layer. The Schottky diode ensures that a conducting channel is completely pinched off when the reverse bias voltage is relatively small, and meanwhile, the Schottky diode can ensure that the Schottky diode has low on-resistance when the Schottky diode is in forward conduction.