3results about How to "Increased avalanche tolerance" patented technology

The utility model relates to the technical field of transistor protection, and discloses a high-voltage MOS terminal protection structure with high avalanche tolerance, which comprises a high-voltage MOS device, the high-voltage MOS device is provided with a cellular area and a terminal protection area, the cellular area is also provided with a shield grid used for reducing on-resistance and increasing breakdown voltage, and the terminal protection area is provided with a terminal protection area. The longitudinal section of the shield grid is arranged in a trapezoid shape, the field limiting rings with the gradually-decreased spacing can widen the width of a depletion region, improve the transverse voltage endurance capability of the MOS device, reduce the peak value of an edge electric field, transfer the peak point of an electric field through a slope field plate and eliminate a grid angle distortion electric field, and the shield grid reconstructs the electric field to be distributed in a trapezoid shape and optimizes a longitudinal electric field. Therefore, the breakdown voltage of the MOS device is improved, and the avalanche trigger threshold is remarkably improved; through the design of the drain buffer layer, a large amount of high-energy carrier kinetic energy can be absorbed, the channel thermal shock can be reduced, the local temperature peak value can be reduced, the two metal layers are utilized to assist heat dissipation, double-path heat conduction is realized, and the avalanche tolerance is improved.

The present invention relates to the technical field of MOSFET devices, and in particular to a super junction MOSFET device and a preparation method thereof, wherein the device comprises: a substrate, M epitaxial layers, a cut-off layer, a well region, a source metal layer, a gate and a drain metal layer; the M epitaxial layers are located on the substrate; the cut-off layer is located on the M epitaxial layers; a well region is provided in the left and right regions of the cut-off layer respectively; the source metal layer and the gate are both located on the cut-off layer, the source metal layer is located on the well region, the gate is located between the source metal layers, and the gate covers the spacing region between the well regions and a part of the well region, and the drain metal layer is located under the substrate; each epitaxial layer is provided with a floating P+ region, the floating P+ region of each epitaxial layer is arranged corresponding to a well region, and the floating P+ regions of two adjacent epitaxial layers are arranged in an alternating manner. The device improves the reliability and stability of the super junction MOSFET device, and enables the device to have better avalanche tolerance and lower on-resistance.

The invention discloses a semiconductor device. The semiconductor device includes: a substrate; a well layer of a second conductivity type; a ring layer of a second conductivity type; a dielectric layer; one part of a plurality of electric connection bulges of the first metal layer penetrates through the first contact hole and is in contact and electric connection with the ring layer, and the other part of the plurality of electric connection bulges of the first metal layer penetrates through the second contact hole and is in contact and electric connection with the well layer; and the second metal layer is at least partially arranged in the second contact hole and is positioned between the electric connection bulge and the well layer. Therefore, the first metal layer and the second metal layer are arranged in the active region, only the first metal layer is arranged in the transition region, the first metal layer is made of copper, and the second metal layer is made of titanium nitride, so that thermal breakdown caused by charge concentration in the active region can be avoided, charge accumulation in the transition region during avalanche breakdown can be improved, and the service life of the device is prolonged. Therefore, the current can flow out of the transition region close to the terminal region more easily to realize current discharge, and the avalanche tolerance of the terminal region of the semiconductor device can be improved.