Trench gate power MOS transistor containing semi-insulating region and preparation method

A MOS transistor and semi-insulating technology, applied in the field of trench gate power MOS transistors and their fabrication, can solve problems such as low avalanche resistance, and achieve the effects of improving breakdown voltage, ensuring threshold voltage, and improving avalanche resistance and robustness.
CN108682684AActive Publication Date: 2018-10-19ANHUI UNIVERSITY OF TECHNOLOGY
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Patent Information

Authority / Receiving Office
CN Β· China
Patent Type
Applications(China)
Current Assignee / Owner
ANHUI UNIVERSITY OF TECHNOLOGY
Publication Date
2018-10-19

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Abstract

The invention discloses a trench gate power MOS transistor containing a semi-insulating region and a preparation method, and belongs to the technical field of high voltage power electronics. The trench gate power MOS transistor containing the semi-insulating region comprises a second conduction type-doped source region, and a first conduction type-doped base region and semi-insulating region, thesecond conduction type-doped source region is located above the first conduction type-doped base region and semi-insulating region which are arranged side by side, and the bottom of the semi-insulating region is in contact with a second conduction type semiconductor-doped drifting layer. The semi-insulating region first adopts ion implantation of impurities of the second conduction type to realizecontra-doping to form an electrically neutral layer, and then the semi-insulating region is formed by ion implantation of amphoteric impurity elements. Aiming at the problem of low UIS avalanche tolerance of a trench gate power MOS transistor in the prior art, the UIS avalanche tolerance and robustness of the trench gate power MOS transistor provided by the invention can be remarkably improved, acapability of resisting large current of the trench gate power MOS transistor is improved, the reliability of the trench gate power MOS transistor is improved, and the breakdown voltage of the trenchgate power MOS transistor is appropriately improved.
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Description

Technical field

[0001] The present invention relates to the technical field of high-voltage power electronics, in particular to a trench gate power MOS transistor containing a semi-insulating region and a preparation method thereof. Background technique

[0002] With the continuous improvement of the performance requirements of power conversion devices, higher requirements are put forward for the power MOS transistor devices that undertake the power conversion function. One of them is the high avalanche tolerance in the unclamped inductive load switching process (UIS) , That is, it has high resistance to UIS avalanche breakdown. This is because the energy stored in the inductive load under UIS conditions is required to be released by the power MOS transistor when it is turned off. At this time, the high current stress in the circuit is very high. It is easy to cause device failure, so the level of avalanche breakdown tolerance is one of the important indicators that reflect the p...

Claims

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