Trench gate super-junction MOSFET device and preparation method therefor

Abstract

The invention relates to a trench gate super-junction MOSFET device and a preparation method therefor. The device comprises a semiconductor substrate and a cellular region positioned in the central region of the semiconductor substrate; the semiconductor substrate comprises a first conductive type substrate and a first conductive type epitaxial layer positioned above the first conductive type substrate; a super-junction structure is arranged in the first conductive type epitaxial layer in the cellular region; second conductive type columns and the first conductive type epitaxial layer can formthe super-junction structure; a cellular trench is formed between the adjacent second conductive type columns; an insulating oxide layer and conductive polysilicon are arranged in each cellular trench; by virtue of the super-junction structure and the trench gate structure, on resistance can be lowered effectively; the first conductive type epitaxial layer outside the cellular trench opening is covered with the insulating oxide layer; the insulating oxide layer outside the cellular trench opening is covered with the conductive polysilicon at the same time; and by virtue of the insulating oxide layer outside the cellular trench opening and the conductive polysilicon, avalanche resistance can be improved, and compact structure and safety and reliability are realized.

Description

Technical field [0001] The invention relates to a MOSFET device and a preparation method thereof, in particular to a trench gate super junction MOSFET device and a preparation method thereof, and belongs to the technical field of semiconductor devices. Background technique [0002] At present, the existing common N-type VDMOS devices include N+ type substrate, N-type epitaxial layer (N-epi), gate oxide layer, poly gate (Poly Gate), P-type body (Pbody); common VDMOS device To improve the withstand voltage, a higher resistivity and thicker N-type epitaxial layer is required, but this will greatly increase the on-resistance of the MOS device. [0003] Existing planar gate super junction MOS devices include N+ type substrate, N-type epitaxial layer (N-epi), P type pillar trench structure (Ppillar trench), gate oxide layer, poly gate (Poly Gate), P Pbody; by introducing a deep trench Trench structure inside the device, the lateral P-type pillar / N-type epitaxial layer can be depleted, w...

AI Technical Summary

Problems solved by technology

[0003] Existing planar gate super junction MOS devices include N+ type substrate, N-type epitaxial layer (N-epi), P-type column deep trench structure (Ppillar trench), gate oxide layer, polysilicon gate (Poly Gate), P Type body region (Pbody); by introducing a deep groove Trench structure inside the device, the lateral P-type column / N-type epitaxial layer depletion can be realized, so that it can be realized under the very low resistivity N-type epitaxial layer High withstand voltage and reduced on-resistance; traditional planar gate super-junction MOSFET, because there is a JFET area in the P-type body interval, it will increase the on-resistance

And due to limitations such as channel length, it is difficult to further reduce the device size

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