11results about How to "Reduce etching" patented technology

The invention discloses a preparation method and application of composite nanoparticles with a gold-silver core-shell structure, and aims to solve the problems that silver halide precipitates are generated on the surface of a silver core and the silver core is etched in the prior art. The thiourea solution is used for replacing a halogen-containing reagent, uniform epitaxial growth of gold on the surface of the silver core is mildly achieved, the gold-shell silver-core nanoparticles which are evenly wrapped and stable in structure are prepared, and the gold-shell silver-core nanoparticles are suitable for the fields of immunodetection and the like and are good in color development effect and low in cost. The method comprises the steps of preparing a gold salt solution, preparing gold nano-seeds, preparing silver nano-cores and generating gold-shell silver-core nano-particles through a chemical reduction reaction, and the problem that a core-shell structure grows unevenly is solved. When the method is applied to immunodetection, the material cost can be remarkably reduced, and a better color development effect can be achieved.

The invention discloses a semiconductor structure processing method, a semiconductor structure and a semiconductor processing device. The processing method comprises the steps that a substrate is provided and comprises a base layer arranged on the substrate, the base layer is provided with a slope structure, the side portion of the base layer gradually extends outwards in the direction from the top surface to the substrate, the slope structure is covered with a cut-off layer, and a dielectric layer is arranged on the cut-off layer; starting a source radio frequency and a bias radio frequency, introducing a first etching gas, and etching the dielectric layer until the third-type hole exposes the cut-off layer; reducing the power of bias radio frequency, so that the openings of the first type of holes, the second type of holes and the third type of holes are laterally etched; and second etching gas is introduced, the cut-off layer exposed by the third type of holes is etched, and the flow of the second etching gas is linearly increased at the slope k along with the etching time until the cut-off layer of the third type of holes is etched to the preset depth. By controlling the allowance of the cut-off layer in the through holes with different depths and different depth-to-width ratios, the process window of the subsequent process of striking the cut-off layer is expanded.

The embodiment of the invention discloses an etching method of a semiconductor material and a control method of an etching machine, and the etching method comprises the steps: providing a semiconductor layer, and carrying out the first etching and the second etching of the semiconductor layer to form a recess; the first etching and the second etching at least comprise the step of bombarding the semiconductor layer by using plasma bias; the plasma bias power in the second etching is smaller than the plasma bias power in the first etching; performing an etching post-processing step, including introducing oxygen-containing gas into the recess to oxidize at least part of the inner wall of the recess; and forming a barrier layer on the inner wall of the recess.

The invention belongs to the technical field of nano material preparation. The invention provides a doped silicon nanowire as well as a preparation device, a preparation method and application thereof, an aluminum chloride generation chamber is arranged in a main reaction chamber of the preparation device and is communicated with a silicon source inlet, a catalytic source inlet and a doping source inlet, and aluminum chloride, the silicon source, the catalytic source and the doping source are mixed in an inner cavity of the main reaction chamber by utilizing the preparation device to prepare the doped silicon nanowire. The method comprises the following steps: adding a silicon source into a catalytic source, carrying out a reaction, reducing the silicon source and the catalytic source into monatomic silicon and a metal catalyst by aluminum monochloride in the reaction process, catalyzing the monatomic silicon by the metal catalyst to generate a silicon nanowire, and carrying out in-situ doping on the silicon nanowire by a doping source to obtain a doped silicon nanowire; the scheme is simple and convenient, doped silicon nanowires can be generated on a large scale, the doping type and the doping effect are controllable, and the improvement effect of doping on the performance of the silicon nanowires is ensured.

The invention relates to the technical field of conductive paste, and provides conductive paste and a solar cell, the conductive paste comprises first silver paste, second silver paste and silver nickel paste, the first silver paste comprises 82-90 parts by weight of first silver powder, 2-6 parts by weight of first glass powder, 0.05-1.0 part by weight of a first auxiliary agent and 6-10 parts by weight of an organic carrier, and the softening point of the first glass powder is 300-400 DEG C; the second silver paste comprises 80-88 parts of second silver powder, 2-6 parts of second glass powder, 0.05-1.0 part of a second auxiliary agent and 5-15 parts of an organic carrier, and the softening point of the second glass powder is 350-450 DEG C; the silver-nickel paste comprises 60-80 parts of silver-nickel metal powder, 3-8 parts of third glass powder, 0.05-1.0 part of a third auxiliary agent and 8-12 parts of an organic carrier, and the softening point of the third glass powder is 400-500 DEG C. Therefore, the conductive paste is low in cost, good in conductivity and free of copper pollution risk.

The invention discloses a method for manufacturing a multi-layer structure and application thereof, and belongs to the field of superconducting quantum chip manufacturing. The method for manufacturing the superconducting quantum chip comprises the steps of manufacturing a multi-layer film on the surface of a substrate, and then performing layer-by-layer patterning on the multi-layer film from the top to the bottom to form a corresponding structure. According to the scheme, the number of etching times in the graphical operation process can be reduced, so that potential damage to other devices or substrates in the chip is reduced, and it is ensured that the performance of the manufactured chip meets the requirement and meets the expectation.

The embodiment of the utility model provides a wafer fixing device and a wafer etching device, and relates to the technical field of semiconductors. The wafer fixing device comprises a bearing disc and an edge ring. The bearing disc is used for placing wafers. The edge ring is arranged around the edge of the bearing disc and comprises a first surface and a second surface which are oppositely arranged, the first surface and the wafer are located on the same side of the bearing disc, and the first surface gradually gets close to the second surface in the direction away from the bearing disc. By performing simple structural deformation on the edge ring, the problem that polymer and reflected plasma are transmitted to the edge of the wafer to cause interference on etching of the edge of the wafer is avoided, and the overall etching uniformity of the wafer is further improved.

Embodiments of the present application provide a wafer stack structure, a manufacturing method thereof and an electronic device. The wafer stack structure comprises a first wafer, a second wafer and a dielectric layer. The first wafer and the second wafer are arranged in a stack, and the dielectric layer covers at least part of a side surface of the second wafer. The dielectric layer is flush with a surface of the second wafer away from the first wafer in a first direction, which is a thickness direction of the wafer stack structure. In the present application, the dielectric layer is deposited at the edge of the wafer during the manufacturing process of the wafer stack structure, which can compensate for the breakage and edge drop of the wafer edge. In the subsequent silicon substrate thinning process, the total thickness variation can be effectively controlled by adjusting the corresponding parameters, thereby reducing the risk of defocusing in the photolithography process, effectively reducing the deviation of the critical dimension at the center position and the edge position, and improving the electrical performance and reliability of the chip stack structure.

The invention provides a method for removing a hard mask layer in a self-aligned multi-pattern process. The method comprises the following steps of: forming a bottom-layer mandrel pattern formed by etching on a front-layer structure and a hard mask layer positioned on the bottom-layer mandrel pattern; forming an etching protection layer covering the bottom core shaft pattern and the hard mask layer, wherein the etching protection layer comprises organic matters; the etching protection layer is etched back until the hard mask layer is completely exposed; etching and removing the hard mask layer by using plasma with a high selection ratio; and removing the etching protection layer by using an ashing process and a wet cleaning method in sequence.

The present invention provides a greenhouse gas treatment device and method based on microwave plasma, comprising an electromagnetic wave input and transmission system, a microwave coupling cavity, an air intake system and an exhaust gas treatment system; the electromagnetic wave input and transmission system comprises two groups of microwave magnetrons and transmission waveguides, and the transmission waveguides are connected to the microwave coupling cavity; the air intake system comprises an Ar input pipeline, an O2 input pipeline, an SF6 input pipeline and a three-layer air intake sleeve; an automatic ignition device is arranged on the side of the three-layer air intake sleeve; the exhaust gas treatment system comprises a closed cavity, an exhaust gas delivery pipeline and a spray device; the microwave coupling cavity can not only improve the ionization effect of SF6 and the utilization rate of microwave power by power coupling, but also improve the ability to treat large flow SF6; the air intake device adopts a three-layer sleeve, which can effectively reduce the etching of the air intake pipe by ionized fluorine ions while improving the SF6 treatment flow, thereby improving the continuous working time.