4results about How to "Reduce etching" patented technology

The invention relates to the technical field of conductive paste, and provides conductive paste and a solar cell, the conductive paste comprises first silver paste, second silver paste and silver nickel paste, the first silver paste comprises 82-90 parts by weight of first silver powder, 2-6 parts by weight of first glass powder, 0.05-1.0 part by weight of a first auxiliary agent and 6-10 parts by weight of an organic carrier, and the softening point of the first glass powder is 300-400 DEG C; the second silver paste comprises 80-88 parts of second silver powder, 2-6 parts of second glass powder, 0.05-1.0 part of a second auxiliary agent and 5-15 parts of an organic carrier, and the softening point of the second glass powder is 350-450 DEG C; the silver-nickel paste comprises 60-80 parts of silver-nickel metal powder, 3-8 parts of third glass powder, 0.05-1.0 part of a third auxiliary agent and 8-12 parts of an organic carrier, and the softening point of the third glass powder is 400-500 DEG C. Therefore, the conductive paste is low in cost, good in conductivity and free of copper pollution risk.

The invention discloses a method for manufacturing a multi-layer structure and application thereof, and belongs to the field of superconducting quantum chip manufacturing. The method for manufacturing the superconducting quantum chip comprises the steps of manufacturing a multi-layer film on the surface of a substrate, and then performing layer-by-layer patterning on the multi-layer film from the top to the bottom to form a corresponding structure. According to the scheme, the number of etching times in the graphical operation process can be reduced, so that potential damage to other devices or substrates in the chip is reduced, and it is ensured that the performance of the manufactured chip meets the requirement and meets the expectation.

The embodiment of the utility model provides a wafer fixing device and a wafer etching device, and relates to the technical field of semiconductors. The wafer fixing device comprises a bearing disc and an edge ring. The bearing disc is used for placing wafers. The edge ring is arranged around the edge of the bearing disc and comprises a first surface and a second surface which are oppositely arranged, the first surface and the wafer are located on the same side of the bearing disc, and the first surface gradually gets close to the second surface in the direction away from the bearing disc. By performing simple structural deformation on the edge ring, the problem that polymer and reflected plasma are transmitted to the edge of the wafer to cause interference on etching of the edge of the wafer is avoided, and the overall etching uniformity of the wafer is further improved.

Embodiments of the present application provide a wafer stack structure, a manufacturing method thereof and an electronic device. The wafer stack structure comprises a first wafer, a second wafer and a dielectric layer. The first wafer and the second wafer are arranged in a stack, and the dielectric layer covers at least part of a side surface of the second wafer. The dielectric layer is flush with a surface of the second wafer away from the first wafer in a first direction, which is a thickness direction of the wafer stack structure. In the present application, the dielectric layer is deposited at the edge of the wafer during the manufacturing process of the wafer stack structure, which can compensate for the breakage and edge drop of the wafer edge. In the subsequent silicon substrate thinning process, the total thickness variation can be effectively controlled by adjusting the corresponding parameters, thereby reducing the risk of defocusing in the photolithography process, effectively reducing the deviation of the critical dimension at the center position and the edge position, and improving the electrical performance and reliability of the chip stack structure.