Manufacturing method for gate and semi-conductor device

Abstract

A method of manufacturing grids includes steps of sequentially forming a grid layer, an anti-reflection layer and grid photoresist patterns on a semiconductor substrate, etching for removing the anti-reflection layer uncovered by the grid photoresist patterns, etching the grid layer uncovered by the anti-reflection layer, and forming grids, wherein a process of etching the anti-reflection layer includes steps of primarily etching the anti-reflection layer with plasma and over-etching the anti-reflection layer with plasma containing CF4 and O2. The invention further provides a method of manufacturing semiconductor devices. The method of manufacturing grids is capable of reducing residue defects of the anti-reflection layer materials or does not have any residue defects.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for manufacturing a gate and a method for manufacturing a semiconductor device. Background technique [0002] With the continuous development of semiconductor integrated circuit manufacturing technology, the line width of semiconductor devices is getting smaller and smaller. At present, the line width of the gate representing the level of photolithography technology has been able to reach 45nm or smaller. A small gate line width can reduce the driving voltage of the formed semiconductor device, thereby reducing power consumption; in addition, it can also reduce the size of the formed semiconductor device, improve the integration level, increase the number of semiconductor devices per unit area, and reduce the power consumption. cost. The Chinese patent application document with the publication number CN 1632921A discloses a gate manufacturing method,...

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Problems solved by technology

[0012] However, the method for etching the anti-reflection layer 16 often produces residual defects of the anti-reflection layer material on the surface of the gate layer 14, such as Figure 5 The residue defect shown in 16b

This defect will affect the subsequent etching of the gate layer 14, and will generate defects after the gate layer 14 is etched, thereby affecting the performance of the semiconductor device formed.

The residual defect can be reduced by extending the overetch time, however, prolonging the overetch time will reduce the yield

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