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Semiconductor structure and formation method thereof

A technology of semiconductor and gate structure, applied in the field of semiconductor structure and its formation, can solve problems such as poor performance of vertical nanowire transistors, and achieve the effects of reduced etching, high integration and simple etching process

Active Publication Date: 2019-07-05
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, the performance of existing vertical nanowire transistors is poor

Method used

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  • Semiconductor structure and formation method thereof
  • Semiconductor structure and formation method thereof
  • Semiconductor structure and formation method thereof

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Embodiment Construction

[0038] There are many problems in the semiconductor structure in the prior art, for example, the performance of the semiconductor structure is poor.

[0039] Now in combination with a semiconductor structure, the reasons for the poor performance of the semiconductor structure are analyzed:

[0040] Due to the large substrate surface occupied by conventional planar transistors, the integration degree of the semiconductor structure is low. In order to increase the integration degree of the formed semiconductor structure, a vertical nanowire transistor is proposed.

[0041] figure 1 and figure 2 It is a structural schematic diagram of each step of a method for forming a vertical nanowire transistor.

[0042] Please refer to figure 1 , a substrate 130 is provided, the surface of the substrate 130 has a fin post 131, and the fin post 131 includes a bottom region I, a channel region II on the bottom region I, and a top portion on the channel region II Zone III.

[0043] conti...

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Abstract

The present invention provides a semiconductor structure and a formation method thereof. The formation method of the semiconductor structure comprises the steps of: providing a substrate, wherein thesubstrate comprises fin columns, and each fin column comprises a bottom portion region, a channel region located on the bottom portion region and a top portion region located on the channel region; forming first isolation layers on the substrate, wherein the first isolation layers cover the bottom portion regions of the fin columns; forming first gate oxide layers and second gate oxide layers at the surfaces of the side walls of the channel regions of the fin columns, wherein the second gate oxide layers are located at the surfaces of the top portions of the first gate oxide layers, and the thicknesses of the first gate oxide layers and the second gate oxide layers are different; forming gate structures at the surfaces of the top portions of the first isolation layers, wherein the gate structures cover the first gate oxide layers and the second gate oxide layers; and forming second isolation layers at the surfaces of the top portions of the gate structures, wherein the second isolationlayers cover the side walls of the top portion regions of the fin columns. The formation method provided by the invention can improve the performances of the semiconductor structure.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration. With the improvement of component density and integration of semiconductor devices, the size of transistors is getting smaller and smaller, and the reduction of transistor size makes the short channel effect more and more significant. [0003] In order to reduce the short channel effect, the fin field effect transistor was born. The gate of the FinFET has a forked 3D structure similar to a fish fin. The gate of the fin field effect transistor can control the switching on and off of the circuit on multiple sides of the fin column, so that the short channel effect of the transistor can be well suppressed. [0004]...

Claims

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Application Information

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IPC IPC(8): H01L21/8234H01L27/088
CPCH01L21/823431H01L21/823462H01L21/823481H01L21/823487H01L27/0886
Inventor 张焕云吴健
Owner SEMICON MFG INT (SHANGHAI) CORP
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