32results about How to "Low-voltage operation" patented technology

An apparatus for redirecting physical energy includes a substrate defining a first boundary of a region, a first electrode defining a second boundary of the region, the second boundary disposed opposite to the first boundary, a second electrode adjacent to the first boundary for cooperating with the first electrode to apply a non-uniform electric field to the region, the non-uniform electric field having electrical field intensities simultaneously including a first electric field intensity and a second electric field intensity, and a layer of material disposed in the region, the layer having a variable index of refraction responsive to the electric field intensities of the non-uniform electric field, the variable index of refraction including a first index of refraction in response to the first electric field intensity and a second index of refraction in response to the second electric field intensity.

A split-gate memory cell, includes an n-channel split-gate non-volatile memory transistor having a source, a drain, a select gate over a thin oxide, and a control gate over a non-volatile gate material and separated from the select gate by a gap. A p-channel pull-up transistor has a drain coupled to the drain of the split-gate non-volatile memory transistor, a source coupled to a bit line, and a gate. A switch transistor has first and second source/drain diffusions, and a gate coupled to the drains of the split-gate non-volatile memory transistor and the p-channel pull-up transistor. An inverter has an input coupled to the second source/drain diffusion of the switch transistor, and an output. A p-channel level-restoring transistor has a source coupled to a supply potential, a drain coupled to the first source/drain diffusion of the switch transistor and a gate coupled to the output of the inverter.

The invention discloses improved structures of light-processing (e.g. light-emitting and light-absorbing/sensing) devices, in particular Vertical Cavity Surface Emitting Lasers (VCSELs), such as may find use in telecommunications applications. The disclosed VSCAL devices and production methods provide for an active region having a quantum well structure grown on GaAs-containing substrates, thus providing processing compatibility for light having wavelength in the range 1.0 to 1.6 μm. The active region structure combines strain-compensating barriers with different band alignments in the quantum wells to achieve a long emission wavelength while at the same time decreasing the strain in the structure. The improved functioning of the devices disclosed results from building them with multicomponent alloy layers having a large number of constituents. The invention discloses as a key constituent in the proposed alloy layers for the active region a substance, such as nitrogen (N), suitable for reducing bandgap energy (i.e., increasing light wavelength) associated with the layers while at the same time lowering the lattice constant associated with the structure and hence lowering strain.

A Random Access Memory (RAM) is provided. The RAM includes a plurality of word-line drivers, at least a first tracking transistor and a second tracking transistor. Each word-line driver has an input node receiving a decoding signal, a power node receiving an operation voltage and a driving node driving a word-line. In an embodiment, the first tracking transistor has two channel terminal nodes respectively coupled to the driving node of one of the word-line driver and a channel terminal node of the second tracking transistor; wherein the first tracking transistor has electronic characteristics tracking those of a driving transistor of word-line driver, and the second tracking transistor has electronic characteristics tracking those of pass-gate transistor(s) in each cell of the RAM.

A multiplexer for selecting a single output signal from a plurality of input signals. For a plurality of complementary input signal pairs in particular, the multiplexer includes for each pair of complementary input signals a control sub-circuit having a selection switch and a common resistance in parallel. The switch and the common resistance have a common low-potential node that is tied to a pair of resistances that are in parallel, wherein each of the parallel resistances is coupled to the respective high-potential nodes of a differential amplifier. A particular pair of incoming complementary input signal pairs controls the differential amplifier. An off-circuit selection signal selects which switch of a plurality of control sub-circuits is activated. When a switch is on, it creates a bypassing of the common resistance, thereby enabling the turn-on of output drivers coupled to the differential amplifier. When a switch is off, the potential drops across the common resistance and the parallel resistances reduce the potential at the output drivers' control nodes enough to block their turn-on. As a result, the only output drivers providing signal output are those associated with the one selected control sub-circuit having its switch turned on.

The present invention provides with an electron-accepting compound having a structure of the following formula (1):

A non-volatile semiconductor memory device includes: a floating gate formed above the semiconductor substrate; an erasing gate formed above the floating gate; a control gate formed above a channel region of a surface layer of the semiconductor substrate at a position corresponding to one lateral side of the floating gate and the erasing gate; a diffusion layer formed on the semiconductor substrate at a position corresponding to another lateral side of the floating gate and the erasing gate; a plug formed above the diffusion layer, the plug coupled to the diffusion layer; a first silicide film formed on an upper surface of the erasing gate; and a second silicide film formed on an upper surface of the plug, in which a height of the upper surface of the plug is flush with/or lower than a height of the upper surface of the erasing gate.

The present invention is intended to prevent a light-emitting diode from emitting light continuously in the case when the level at an input terminal is fixed high because of software or the like and to avoid various problems, such as battery exhaustion and breakdown of the light-emitting diode, in PDAs, cellular phones, etc. For these purposes, a high-pass filter 21 for passing the high-frequency components of an optical transmission input signal having a pulse waveform and a binary circuit 22 for binarizing the output signal of the high-pass filter 21 so as to be returned to a pulse waveform are provided in the preceding stage of a light-emitting device driving circuit 23 for driving a light-emitting diode 8 for optical transmission.

In an SRAM, memory cells are each constructed of four NMOS transistors and two PMOS transistors 25 and 26. The four NMOS transistors are each constructed of DTMOS in which the channel region is electrically connected to the gate. In each NMOS transistor, a threshold voltage Vth is lower in an ON stage than in an OFF stage. The threshold voltage Vth in the OFF stage is equivalent to that of an ordinary NMOS transistor in which the channel region is not electrically connected to the gate. Read and write circuits of the SRAM also include MOS transistors formed of DTMOS in which the channel region is electrically connected to the gate.

Microelectronic structures and devices, and method of fabricating a three-dimensional microelectronic structure is provided, comprising passing a first precursor material for a selected three-dimensional microelectronic structure into a reaction chamber at temperatures sufficient to maintain said precursor material in a predominantly gaseous state; maintaining said reaction chamber under sufficient pressures to enhance formation of a first portion of said three-dimensional microelectronic structure; applying an electric field between an electrode and said microelectronic structure at a desired point under conditions whereat said first portion of a selected three-dimensional microelectronic structure is formed from said first precursor material; positionally adjusting either said formed three-dimensional microelectronic structure or said electrode whereby further controlled growth of said three-dimensional microelectronic structure occurs; passing a second precursor material for a selected three-dimensional microelectronic structure into a reaction chamber at temperatures sufficient to maintain said precursor material in a predominantly gaseous state; maintaining said reaction chamber under sufficient pressures whereby a second portion of said three-dimensional microelectronic structure formation is enhanced; applying an electric field between an electrode and said microelectronic structure at a desired point under conditions whereat said second portion of a selected three-dimensional microelectronic structure is formed from said second precursor material; and, positionally adjusting either said formed three-dimensional microelectronic structure or said electrode whereby further controlled growth of said three-dimensional microelectronic structure occurs.

The invention discloses a low power ideal diode control circuit. In described examples of a circuit (100) that operates as a low-power ideal diode, the circuit (100) includes a p-channel transistor (102) connected to receive an input voltage (VIN) on a first terminal and to provide an output voltage (VOUT) on a second terminal, a first amplifier (106) connected to receive the input voltage and the output voltage and to provide a first signal that dynamically biases a gate of the p-channel transistor (102) as a function of the voltage across the p-channel transistor, and a second amplifier (104) connected to receive the input voltage and the output voltage and to provide a second signal that operates to turn off the gate of the p-channel transistor (102) responsive to the input voltage (VIN) being less than the output voltage (VOUT).

The semiconductor memory device of the invention includes 2 TFT MOS transistors, 2 bulk MOS transistors, a first and second access MOS transistors and a first and second capacitor. The TFT and bulk MOS transistors form a latch for retaining a data that is inverted between a first and second node. The first bulk access MOS transistor switches the first node to connect to a first bit line according to a voltage of a word line. The second bulk access MOS transistor, switches the second node to connect to a second bit line according to the voltage of the word line. The first capacitor is disposed between the first node and a power supply voltage. The second capacitor is disposed between the second node and the power supply voltage. The bulk MOS transistors and the access MOS transistors are formed by a recess gate type MOS transistor.