Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Power semiconductor device and preparation method thereof

A technology of power semiconductors and devices, which is applied in the field of power semiconductor devices and their preparation, and can solve problems affecting the avalanche tolerance of devices

Pending Publication Date: 2021-01-26
湖南国芯半导体科技有限公司
View PDF3 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In view of the above problems, the present disclosure provides a power semiconductor device and its preparation method, which solves the problem that the avalanche current discharge path of the power semiconductor device flows through the base region of the parasitic npn transistor in the prior art and the long path affects the avalanche tolerance of the device. question

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Power semiconductor device and preparation method thereof
  • Power semiconductor device and preparation method thereof
  • Power semiconductor device and preparation method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0053] Such as Figure 4 As shown, the embodiment of the present disclosure provides a power semiconductor device 200 , including a substrate 201 , an epitaxial layer 202 , a drain metal layer 203 , an active region 210 , a transition region 220 and a terminal region 230 .

[0054] Exemplarily, the substrate 201 is a silicon carbide substrate or a silicon substrate of the first conductivity type. The resistivity of the substrate 201 is 0.01 to 0.03 Ω·cm, and the thickness is 200 to 400 μm.

[0055] The epitaxial layer 202 is an epitaxial layer of the first conductivity type and is located above the substrate 201 . The ion doping concentration of the epitaxial layer 202 is 5e14 to 5e16 cm -3 . The doping concentration and thickness of the epitaxial layer 202 are adjusted according to different device withstand voltage capabilities.

[0056] The drain metal layer 203 is located under the substrate 201 and forms an ohmic contact with the substrate 201 .

[0057] The active r...

Embodiment 2

[0078] On the basis of the first embodiment, this embodiment provides a method for manufacturing a power semiconductor device 200 . Figure 6 It is a schematic flowchart of a manufacturing method of a power semiconductor device 200 shown in an embodiment of the present disclosure. Figure 7-Figure 12 It is a schematic cross-sectional structure formed by related steps of a method for manufacturing a power semiconductor device 200 shown in an embodiment of the present disclosure. Below, refer to Figure 6 and Figure 7-Figure 12 The detailed steps of an exemplary method of the method for manufacturing the power semiconductor device 200 proposed by the embodiment of the present disclosure will be described.

[0079] Such as Figure 6 As shown, the manufacturing method of the power semiconductor device 200 in this embodiment includes the following steps:

[0080] Step S101 : providing a first conductivity type substrate 201 .

[0081] The substrate 201 is a silicon carbide su...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a power semiconductor device and a preparation method thereof. The power semiconductor device comprises an active region, a terminal region and a transition region, wherein theactive region and the terminal region are arranged on an epitaxial layer; the transition region is positioned between the active region and the terminal region; and the active region comprises a plurality of second conductive type well regions arranged in the surface of the epitaxial layer at intervals, grooves formed in the surfaces of the well regions, first conductive type source regions located in the surfaces of the well regions and located on the two sides of the grooves, and second conductive type short circuit regions located in the well regions and located below the grooves, wherein the bottom of the well region is provided with a recessed structure at a position corresponding to the grooves. By forming the concave structure at the bottom of the well region at the position corresponding to the trench, the avalanche breakdown position is transferred from the terminal region to the active region with a larger area, the heat dissipation area is increased, the avalanche current path avoids the parasitic npn transistor base region, the avalanche current path is shortened, the generation of heat is reduced, and the avalanche tolerance is improved.

Description

technical field [0001] The present disclosure relates to the technical field of semiconductor devices, in particular to a power semiconductor device and a manufacturing method thereof. Background technique [0002] Power semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), in switching applications, inductive loads and parasitic inductance are not clamped intentionally or unintentionally, and the power device is turned on When it is turned off instantly, the energy stored in the inductance when the loop is turned on must be released by the power device at the moment of turn off. Due to the sudden change of the MOSFET drain current, the inductance generates a large induced electromotive force and superimposes on the power supply voltage, prompting The power device is subjected to a large voltage, is in an avalanche state and flows a large current, resulting in a large power loss. Once th...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/786H01L29/06H01L21/336
CPCH01L29/78606H01L29/0626H01L29/0657H01L29/78642H01L29/78645H01L29/66742
Inventor 高秀秀李诚瞻齐放戴小平
Owner 湖南国芯半导体科技有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products