Power semiconductor device and preparation method thereof

A technology of power semiconductors and devices, which is applied in the field of power semiconductor devices and their preparation, and can solve problems affecting the avalanche tolerance of devices
CN112271218APending Publication Date: 2021-01-26湖南国芯半导体科技有限公司

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
湖南国芯半导体科技有限公司
Publication Date
2021-01-26

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Abstract

The invention provides a power semiconductor device and a preparation method thereof. The power semiconductor device comprises an active region, a terminal region and a transition region, wherein theactive region and the terminal region are arranged on an epitaxial layer; the transition region is positioned between the active region and the terminal region; and the active region comprises a plurality of second conductive type well regions arranged in the surface of the epitaxial layer at intervals, grooves formed in the surfaces of the well regions, first conductive type source regions located in the surfaces of the well regions and located on the two sides of the grooves, and second conductive type short circuit regions located in the well regions and located below the grooves, wherein the bottom of the well region is provided with a recessed structure at a position corresponding to the grooves. By forming the concave structure at the bottom of the well region at the position corresponding to the trench, the avalanche breakdown position is transferred from the terminal region to the active region with a larger area, the heat dissipation area is increased, the avalanche current path avoids the parasitic npn transistor base region, the avalanche current path is shortened, the generation of heat is reduced, and the avalanche tolerance is improved.
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Description

technical field

[0001] The present disclosure relates to the technical field of semiconductor devices, in particular to a power semiconductor device and a manufacturing method thereof. Background technique

[0002] Power semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), in switching applications, inductive loads and parasitic inductance are not clamped intentionally or unintentionally, and the power device is turned on When it is turned off instantly, the energy stored in the inductance when the loop is turned on must be released by the power device at the moment of turn off. Due to the sudden change of the MOSFET drain current, the inductance generates a large induced electromotive force and superimposes on the power supply voltage, prompting The power device is subjected to a large voltage, is in an avalanche state and flows a large current, resulting in a large power loss. Once th...

Claims

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