Power semiconductor device and manufacturing method thereof

Abstract

The invention relates to a power semiconductor device and a manufacturing method thereof. The manufacturing method comprises the a step of well injection, and is characterized in that an injection blocking layer in the step of well injection comprises a strip-shaped injection blocking structure located between two adjacent grid electrodes, the bottom of a well region below the injection blocking structure is enabled to form a recess sinking into the well region upward after well injection and diffusion, the extending direction of the strip-shaped injection blocking structure is perpendicular to the spacing direction of the two adjacent grid electrodes, and the width of the injection blocking structure is less than the width of a metal interconnecting wire connected with a source region at the source region connecting part. When the power semiconductor device is turned off in an inductive load circuit, hole current flowing from the recess is short in path to source metal, and the hole current can directly get into the source metal, so that the possibility of getting into the source region is reduced, a parasitic NPN transistor is enabled to be difficult to open, and thus the avalanche tolerance of the device is increased.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a power semiconductor device and a method for manufacturing the power semiconductor device. Background technique [0002] Due to the particularity of the use environment and conditions of use, modern electronic circuits have higher and higher requirements for the reliability of power semiconductor devices. Power semiconductor devices (power VDMOS, power IGBT, etc.) are often connected to inductive load circuits due to the needs of use. When the device is turned off, the inductance on the inductive load can generate a voltage twice the power supply voltage applied to the load circuit, which is added between the drain and source of the device, causing the drain and source of the device to withstand a large current impact. When the drain voltage increases and cannot be pinched off, the device enters the avalanche region. At this time, the drain-body diode will generate cu...

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Problems solved by technology

[0004] 1. Although increasing the implantation dose of the P well can increase the avalanche tolerance, it will increase the turn-on voltage VTH, and more seriously, it will increase the on-resistance Rdon, which will increase the temperature rise of the device, thereby reducing the reliability of the device

[0005] 2. P+ injection after N+ injection will also increase the turn-on voltage VTH, and increase the on-resistance Rdon, which will increase the temperature rise of the device, thereby reducing the reliability of the device

The reason is that the impurity boron ions implanted during this P+ implantation are close to the channel of the device, and the boron ions will diffuse into the channel in the subsequent diffusion process, thereby increasing the turn-on voltage VTH and increasing the on-resistance Rdon

[0006] 3. Increasing the number of cells will increase the area of ​​the chip, thereby increasing the manufacturing cost

[0007] 4. Although P+ implantation after contact hole etching will improve the device burnout caused by poor contact of individual cells in the device, due to the limited size of the contact hole in general, the area of ​​P-type impurities implanted through the contact hole If it is not large enough, the reduction of the resistance Rb of the device body region is limited, so that the improvement of the avalanche resistance is not large enough, so this method is not efficient in improving the avalanche resistance of the device

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