Discrete power mos field effect transistor and manufacturing method thereof

Abstract

The invention discloses a discrete power mos field effect transistor and a manufacturing method thereof. In the process of forming the power mos field effect transistor, a source region is firstly formed in an epitaxial layer, contact hole corrosion is carried out on the formed source region, P+ injection and original P+ region connection are carried out on a contact hole region to form a P+ region, metal deposition is carried out to form a metal layer and contact of the metal layer and N+ and P+ of the source region is finally obtained. In the technical process, the lithography process of separately forming N+ and P+ through twice lithography corrosion in the original technical process is reduced, so that one-time lithography is reduced from the manufacturing process of a power MOS, and the manufacturing process is simplified and the production cost is reduced; a contact path of the P+ and the metal layer is shortened by adopting a silicon etching technology, so that parasitic P+ resistance is reduced to inhibit starting of a parasitic NPN and improvement of the avalanche breakdown tolerance is facilitated; and the source region is firstly formed and then contact hole corrosion is carried out on the formed source region, so that the trouble that P+ injection cannot be carried out after contact hole lithography due to the fact that the concentration of the N+ is much greater than that of the P+ is avoided.

Description

technical field [0001] The invention relates to a semiconductor power device, in particular to a discrete power mos field effect transistor and a manufacturing method thereof. Background technique [0002] Traditional discrete power mosfet manufacturing methods usually include 7-layer lithography termination ring lithography, active area lithography, polysilicon lithography, N+ lithography, contact hole lithography, metal lithography and passivation layer lithography A total of 7 layers of lithography, and N+ lithography is needed to determine the N+ implantation area during N+ implantation, otherwise, the P+ area that should not be implanted will be implanted with N+, because usually the N+ concentration is much higher than the P+ concentration, which will lead to If the P+ implantation after contact hole photolithography cannot be formed, the P+ contact region cannot be formed, and the process is cumbersome and difficult to form, such as figure 1 shown. The complexity an...

AI Technical Summary

Problems solved by technology

[0002] Traditional discrete power mosfet manufacturing methods usually include 7-layer lithography termination ring lithography, active area lithography, polysilicon lithography, N+ lithography, contact hole lithography, metal lithography and passivation layer lithography A total of 7 layers of lithography, and N+ lithography is needed to determine the N+ implantation area during N+ implantation, otherwise, the P+ area that should not be implanted will be implanted with N+, because usually the N+ concentration is much higher than the P+ concentration, which will lead to If the P+ implantation after contact hole photolithography cannot be formed, the P+ contact region cannot be formed, and the process is cumbersome and difficult to form, such as figure 1 shown

Images