Super junction MOS (Metal Oxide Semiconductor) type power semiconductor device and preparation method thereof

Abstract

The invention relates to a super junction MOS (Metal Oxide Semiconductor) type power semiconductor device and a preparation method thereof, and belongs to the technical field of power semiconductors.The invention provides a power semiconductor device which comprises a multi-layer first conduction type semiconductor column region and uses a heterojunction as an unbalanced carrier barrier, realizesa charge balance effect, reduces the high injection efficiency at one side of a source electrode, solves the problems of reduced breakdown voltage and deteriorated reverse recovery characteristic ofa body diode caused by charge imbalance brought about by the actual process, improves the breakdown voltage of the device and improves the reverse recovery characteristic of the body diode. In addition, the invention further provides a preparation method of the super junction MOS type power semiconductor device, which is simple and controllable in manufacturing process and has strong compatibilitywith the existing process.

Description

technical field [0001] The invention belongs to the technical field of power semiconductors, and in particular relates to a super-junction MOS power semiconductor device and a preparation method thereof. Background technique [0002] figure 1 The half-cell structure of a traditional Super Junction Metal Oxide Semiconductor Field Effect Transistor (SJ-MOSFET) is shown. SJ-MOSFET is a multi-subtype device controlled by an insulated gate. There are P-type pillar regions and N-type pillar regions with opposite doping types in the region, and the charge balance effect brought by them can improve the breakdown voltage of the device. However, in the actual process, the process of etching the P-type pillar regions will It presents a certain angle, so that the groove of the etched P-type column area is trapezoidal. This trapezoidal groove will cause the charge imbalance between the P-type column area and the N-type column area, thereby reducing the breakdown voltage of the device. ...

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Problems solved by technology

[0002] figure 1 The half-cell structure of a traditional Super Junction Metal Oxide Semiconductor Field Effect Transistor (SJ-MOSFET) is shown. SJ-MOSFET is a multi-subtype device controlled by an insulated gate. There are P-type pillar regions and N-type pillar regions with opposite doping types in the region, and the charge balance effect brought by them can improve the breakdown voltage of the device. However, in the actual process, the process of etching the P-type pillar regions will It presents a certain angle, so that the groove of the etched P-type column area is trapezoidal. This trapezoidal groove will cause the charge imbalance between the P-type column area and the N-type column area, thereby reducing the breakdown voltage of the device.

In addition, due to the structural characteristics of the super-junction MOSFET and the high injection efficiency on the source side, a large number of non-equilibrium carriers will be stored in the drift region during the reverse conduction process, and a large number of non-equilibrium carriers will increase the bulk density. The reverse recovery time of the diode increases the turn-off loss, which deteriorates the reverse recovery characteristics of the body diode in the MOSFET

Therefore, there is an urgent need for a new super-junction MOS power semiconductor device to solve the problems of reduced breakdown voltage and worsened reverse recovery characteristics of the body diode caused by the charge imbalance caused by the actual process.

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