A mosfet structure and its manufacturing method

A manufacturing method and stacking technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems affecting device performance and other issues

Active Publication Date: 2016-03-23
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] As the voltage between the source and drain increases, the electric field where the carriers in the pinch-off region is also increases, so the electrons can obtain higher speed and greater energy, and generate a certain number of hot carriers. When the electric field in the pinch-off region increases to a certain extent, these hot carriers have a certain probability to cross the barrier between the channel and the gate dielectric layer and enter the gate dielectric layer, thereby introducing defects and traps in the gate dielectric layer , affecting device performance

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  • A mosfet structure and its manufacturing method
  • A mosfet structure and its manufacturing method
  • A mosfet structure and its manufacturing method

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Embodiment Construction

[0023] In order to make the object, technical solution and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0024] Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

[0025] Such as Figure 5 As shown, the present invention provides an asymmetric MOSFET structure, including: a substrate 100; a gate stack 500 located above the substrate 100; source and drain located in the substrate on both sides of the gate stack 500 region 200; sidewalls 160 on both sides of the gate stack 500;...

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Abstract

The present invention provides a method of manufacturing a MOSFET, comprising: a. providing a substrate (100), a source / drain region (200), a pseudo-gate stack (150), an interlayer dielectric layer (300), and a sidewall (160); b. removing the pseudo-gate stack (150) to form a pseudo-gate vacancy; c. performing inclined ion injection on the semiconductor structure, and forming a carrier scattering region (400), the carrier scattering region (400) being located below a surface of the semiconductor structure on a side of a drain; and d. depositing a gate stack layer (500) in the pseudo-gate vacancy. According to the method for reducing a probability of hot carrier transition provided by the present invention, scattering impurities, that is, non-ionized impurities are injected in a channel material near a side of a drain, so that a probability that a hot carrier is scattered in a pinch-off region is increased, a carrier is subject to increased resistance in the movement in the pinch-off region, the energy of a hot carrier is reduced, and accordingly the quantity and probability of hot carriers that enter a gate dielectric layer are reduced.

Description

technical field [0001] The invention relates to a MOSFET structure and a manufacturing method thereof. More particularly, it relates to a MOSFET structure for reducing the number of hot electrons in a channel near the drain and a method of manufacturing the same. technical background [0002] When the MOSFET is in the saturation region, the channel inversion layer is partially pinched off, that is, the inversion carrier concentration on the channel surface near the drain end is very small, and the resistance is large. According to the series voltage division relationship, the voltage in the channel region is mostly Falling on the pinch-off region, a large electric field is generated in the pinch-off region. When the anti-type carriers in the channel region move to the boundary of the pinch-off region under the action of the electric field, they will be accelerated by the electric field of the pinch-off region, and will be quickly swept to the drain end. During this process,...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/265H01L29/78H01L29/10
CPCH01L29/66545H01L21/26506H01L21/26586H01L29/1045H01L29/4966H01L29/66659H01L29/7835
Inventor 尹海洲刘云飞
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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