37 results about "Application-specific instruction-set processor" patented technology

A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. A multi-stage data stream based processor incorporates a parallel/pipelined architecture optimized to perform data stream processing efficiently. The multi-stage parallel/pipelined processor provides significantly higher processing speeds by combining multiple RCUs wherein input data samples are input in parallel to all RCUs while computation results from one RCU are used by adjacent downstream RCUs. A register file provides storage for historical values while local storage in each RCU provides storage for temporary results.

The invention discloses an ASIP based on an extensible processor architecture and a realizing method thereof, which mainly solve the problem of high circuit complexity and large resource consumption in the prior art. Aiming at the extensible processor architecture after optimization, the invention adopts a five-level-pipeline realizing method, and adopts a data orientation technology and a branch non-execution strategy to solve data hazards and control hazards in pipeline treatment respectively. The ASIP comprises an instruction fetch unit, a decoding unit, an execution unit, a memory access unit, a write-back unit, a pipeline control unit, a timer and an interrupt controller. According to the ASIP and the method, the characteristics of a pipeline processor and an FPGA (field-programmable gate array) are considered sufficiently, the pipeline structure is partitioned reasonably, and the hardware resources of the FPGA are utilized to the utmost extent; and the ASIP and the method have the advantages of simple circuit design, low resource consumption, high processor performance and low power consumption, and are highly suitable for large-scale parallel processing.

Provides methods, systems and apparatus for coupling a general purpose processor (GPP) to an application specific instruction set processor (ASIP) in such a manner that the GPP can include execute instructions that do not normally comprise part of its instruction set architecture (ISA). The GPP is coupled to the ASIP via a coprocessor port such that instructions issued by the GPP to the port are conveyed to a novel pre-decoder module of the ASIP. The pre-decoder module translates the GPP instruction into operation codes for ASIP instructions to be executed in the ASIP or to an address in the ASIP instruction memory that identifies a start address for a plurality of ASIP instructions defining a complex application specific function. Once the ASIP has executed the instructions it shares the result of the execution with the GPP. In this way, the GPP takes advantage of the ASIP in its ability to more quickly execute an application specific program/procedure.

The invention provides an instruction set encoding method based on an embedded special instruction set processor, comprising five steps of: defining machine code bit wide, defining instruction type, a defining addressing mode, a dividing instruction code filed and encoding. The instruction set is optimized according to the characteristic that both an internal memory and a data bus resource of a Field Programmable Gate Array (FPGA) take 18 bits as basic bit wide. The instruction set comprises 16 pieces of multifunctional instructions in the types of arithmetic and logic operation, data interchange and program sequencing, wherein the instructions comprise protective instruction fields required for constructing a single instruction stream-multiple data stream concurrent processing system with instruction independency capability. The instruction set disclosed by the invention has integral and simplified application models; under the two application models, the code length of an instruction machine can be respectively shortened to 16-bit and 14-bit so that the utilization efficiency of an internal circuit resource of the FPGA and the instruction execution speed of a processor are greatly improved.

The invention relates to a specific processor system structure for a high-performance programmable controller and an implementation method of the dedicated processor system structure. The specific processor system structure comprises a PLC (Programmable Logic Controller) specific instrument set processor and a general processor, wherein the PLC specific instrument set processor is connected with a general processor through the PLC specific instrument set processor and an interface of the general processor. The implementation method comprises a four-level flow line consisting of a fetch stage,a decoding stage, an executing stage and a writing-back stage, according to the PLC specific instrument set processor. By designing the PLC specific instrument set which accords with the PLC instrument characteristics, the number of instruments for executing a PLC processor is reduced, the execution speed of a PLC program is accelerated, and the processing performance of the PLC processor to a functional block is improved.

The invention discloses an assembler designing method based on a specific instruction set processor for very long instruction words. Improving of an assembler is realized by designing functions of register renaming and instruction packing and scheduling. The method includes that after write-after-write collisions are detected in instructions by the register renaming, a register always being idle is searched to replace a destination register in the instructions to eliminate the write-after-write collisions; the instruction packing and scheduling design are executed simultaneously, the assembler packs instructions while detects collisions among the instructions and eliminates the instruction collisions according to an executing sequence of an instruction scheduling adjusting instruction, and the instruction packing and scheduling design include steps of program segmentation, intra-segment instruction packing and scheduling, intersegment instrument collision detecting and adjusting, skip instruction label matching, skip instruction collision detecting and adjusting and skip instruction label rematching. By the assembler designing method based on the instruction set processor special for the very long instruction words, instruction-level parallelism of the assembler is improved, and application fields of the application specific instruction set process based on the very long instruction words are greatly expanded.

The invention provides a space-borne real-time parallel data processing system aiming at the characteristics of huge data volume and high real-time processing requirements of the space-borne system. The system mainly consists of a power supply subsystem, a dedicated instruction set processor parallel processing array subsystem, and a data distribution-driven synthesis subsystem to form a three-layer processing platform structure. The data distribution-driven synthesis subsystem is used to complete the preprocessing and processing of input data The result output is located in the middle layer of the entire processing platform; the special-purpose instruction set processor parallel processing array subsystem is located on the top layer of the entire processing platform, and the special-purpose instruction set processor is used to form a parallel processing array to complete the processing of input data; the power supply subsystem The system provides power for the entire system and is located at the bottom of the entire processing platform; the three subsystems are connected through a dedicated bus layer. The invention has the advantage of being able to realize real-time parallel fast processing of massive data on the satellite, and can be used for denoising and compressing distributed images on the satellite.

The invention discloses a parameterized specific instruction set processor design platform comprising a universal register number selection module, a bus bit width selection module, a data memory type selection module, a program control instruction selection module, an arithmetical logical operation instruction selection module, a target processor generation module and a retargetable assembler. The design platform generates the optimal specific instruction set processor core which saves most resources in the structure frame of the specific instruction set processor core according to related parameters selected by a user for different application fields, and also shortens the design period of the specific instruction set processor. The retargetable assembler is capable of positioning the compiler to the target processor according to the parameters selected by the user, and further capable of translating an assembler source program into the machine codes of the target processor; as a result, the work load of a programmer is reduced; therefore, the working efficiency is improved.

A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.

The invention provides an application program and special instruction set integrated processor agile design method. The method comprises the following steps: establishing an application and test environment of an application program to be operated on a processor; formulating a processor expansion architecture and an expansion description rule, representing basic expansion units in the processor byusing a specified data type, and representing an expansion instruction in the processor by using an expansion instruction definition function; compiling an expansion instruction definition function under the formulated processor expansion architecture and the expansion description rule; and realizing the hot spot part of the application program by using the expansion instruction definition function. The processor expansion instruction is described by adopting an advanced programming language, so that a general engineer can effectively master the processor expansion instruction. The definitionof the processor extension instruction only comprises an operation definition, and details for realizing the instruction in the processor micro-architecture are not involved. Integrated research anddevelopment of processor extension instructions and application programs are achieved, and a development environment in a rapid cycle of definition, use and verification of the expansion instructionsis achieved.

The invention discloses a logical resource sharing method for a special instruction set processor. The method comprises steps of S1, an optimal transformation set being partitioned, and a similarity matrix R being partitioned according to columns; S2, for unshielded elements of each block, scanning the value of each element line by line from the first row and the first column, and searching the maximum element value gamma i, j appearing for the first time as a growth point for further expansion; S3, searching a maximum element value gamma i, a appearing for the first time in the ith row indicated by the coordinates (i, j) of the growing points, searching a maximum element value gamma j, b appearing for the first time in the jth row, and then shielding all element values in the ith row and the jth row; S4, judging the newly found element values gamma i, a and gamma j, b, and if all the elements are 0, continuing; otherwise, shielding or repeating the step; and S5, grouping and archiving the calculation modes generated in the step S4. The method has advantages of being simple in principle, easy to implement, capable of improving calculation efficiency and resource utilization rate and the like.