37 results about "Application-specific instruction-set processor" patented technology

A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.

A novel and useful apparatus for and method of spur reduction using computation spreading with dithering in a digital phase locked loop (DPLL) architecture. A software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU is adapted to spread the computation of the atomic operations out over a PLL reference clock period wherein each computation is performed at a much higher processor clock frequency than the PLL reference clock rate. This significantly reduces the per cycle current transient generated by the computations. The frequency content of the current transients is at the higher processor clock frequency which results in a significant reduction in spurs within sensitive portions of the output spectrum. Further reduction in spurs is achieved by dithering the duration of the software loop of atomic operations and / or by randomly shuffling one or more non-data dependent instructions within each iteration of the software loop.

This invention is an application specific integrated processor to implement the complete fixed-rate DRX signal processing paths (FDRX) for a reconfigurable processor-based multi-mode 3G wireless application. This architecture is based on the baseline 16-bit RISC architecture with addition functional blocks (ADU) tightly coupled with the based processor's data path. Each ADU accelerates a computation-intensive tasks in FDRX signal path, such as multi-tap FIRs, IIRs, complex domain and vectored data processing. The ADUs are controlled through custom instructions based on the load / store architecture. The whole FDRX data path can be easily implemented by the software employing these custom instructions.

A novel and useful apparatus for and method of spur reduction using computation spreading in a digital phase locked loop (DPLL) architecture. A software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU is adapted to spread the computation of the atomic operations out over and completed within an entire PLL reference clock period. Each computation being performed at a much higher processor clock frequency than the PLL reference clock rate. This functions to significantly reduce the per cycle current transient generated by the computations. Further, the frequency content of the current transients is at the higher processor clock frequency. This results in a significant reduction in spurs within sensitive portions of the output spectrum.

The invention discloses an extensible ASIP structure platform and an instruction processing method. The platform is provided with an assembly line of instruction execution logic, the instruction execution logic comprises n clusters, the clusters 0-(n-2) are conventional clusters and used for achieving conventional instructions, and each cluster comprises two arithmetic logic units ALU and a 4-read-2-write distributed register file RF; the cluster n-1 is an extension cluster, is used for realizing a special extension instruction, and comprises an ERF (Extended Register Function) with 6 read ports, 2 write ports and at most 32 universal registers, an EFU (Extended Function Unit) with 6 inputs and 2 outputs, and an arithmetic logic unit ALU (Arithmetic Logic Unit); an outflow control networkunit ICN and an operand transfer network unit OPN are included between the clusters; and the execution management unit EMU coupled with each ALU or EFU and the register management unit RMU coupled with each RF or ERF form hardware of an instruction execution control mechanism. According to the method, instruction processing is completed based on the platform. The method has the advantages of beingeasy to implement, capable of improving the expansibility of the special instruction set processor and the like.

The invention relates to a specific processor system structure for a high-performance programmable controller and an implementation method of the dedicated processor system structure. The specific processor system structure comprises a PLC (Programmable Logic Controller) specific instrument set processor and a general processor, wherein the PLC specific instrument set processor is connected with a general processor through the PLC specific instrument set processor and an interface of the general processor. The implementation method comprises a four-level flow line consisting of a fetch stage,a decoding stage, an executing stage and a writing-back stage, according to the PLC specific instrument set processor. By designing the PLC specific instrument set which accords with the PLC instrument characteristics, the number of instruments for executing a PLC processor is reduced, the execution speed of a PLC program is accelerated, and the processing performance of the PLC processor to a functional block is improved.

The invention relates to a method for designing a specific instruction set processor, and the method can make the accuracy performance evaluation at the beginning of designing a chip, advance the testof a specific application, speed up the design process and reduce the re-design possibility which is because the performances of the chip can not achieve the requirements. The method establishes an LISA processor model at the early stage of the design, generates a corresponding software tool by the LISA model, builds up a virtual prototyping platform which is similar to the performances of real hardware on an ARM ESL, including a AHB bus model with precise cycle, an EMI model and an SDRAM model which are needed for designing the platform, searches out the performances under the different situations by repairing the models of the processor, obtains an optical software / hardware dividing method, directly verifies on the models and speeds up the design cycle of the processor.