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Assembler designing method based on specific instruction set processor for very long instruction words

A technology of super-long instruction words and special instructions, applied in the direction of concurrent instruction execution, machine execution devices, etc., can solve the problems of increasing the workload of designers, increasing the design and implementation cycle, etc., to improve design efficiency, improve parallelism, and expand applications. field effect

Inactive Publication Date: 2013-05-22
XIDIAN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For the special instruction set processor ASIP, this not only increases the workload of the designer, but also increases the implementation cycle of the design

Method used

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  • Assembler designing method based on specific instruction set processor for very long instruction words
  • Assembler designing method based on specific instruction set processor for very long instruction words
  • Assembler designing method based on specific instruction set processor for very long instruction words

Examples

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Effect test

Embodiment 1

[0020] Example 1: Register renaming process

[0021] refer to figure 1 , the implementation of register renaming requires instruction write-after-write conflict detection. If a write-after-write conflict is found in the instruction, check whether there are free registers and determine whether the free registers are all free during the replacement of conflicting registers in these instructions. Yes, if there are free registers and they are always free, register renaming can be used to eliminate write-after-write conflicts. A register is free from the last time it is called until it is reassigned, and can be used for renaming. How to judge whether a register is free? For this problem, we create a register state table, and analyze the use of registers between different instructions to create a state table. When you encounter a register that needs to be renamed, that is, a register with a write-after-write conflict, you can look up the status table to determine whether there is...

Embodiment 2

[0038] Embodiment 2: Instruction packaging and scheduling design method

[0039] In the process of instruction packaging and scheduling, the execution order of instructions before and after the jump instruction needs to be protected. This protection is mainly through the following two methods:

[0040] Instructions that appear before the jump instruction cannot be placed after the jump instruction;

[0041] Instructions that appear after a jump instruction cannot be placed before the jump instruction.

[0042] For the protection of the execution order of instructions before and after the jump instruction, the correct execution order of the instructions is mainly ensured by means of program segmentation. The instruction packaging and scheduling process of the entire program is as follows: figure 2 shown. First, the whole program is segmented according to the jump instruction and the target label. After the program is segmented, the instruction scheduling in the segment is n...

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Abstract

The invention discloses an assembler designing method based on a specific instruction set processor for very long instruction words. Improving of an assembler is realized by designing functions of register renaming and instruction packing and scheduling. The method includes that after write-after-write collisions are detected in instructions by the register renaming, a register always being idle is searched to replace a destination register in the instructions to eliminate the write-after-write collisions; the instruction packing and scheduling design are executed simultaneously, the assembler packs instructions while detects collisions among the instructions and eliminates the instruction collisions according to an executing sequence of an instruction scheduling adjusting instruction, and the instruction packing and scheduling design include steps of program segmentation, intra-segment instruction packing and scheduling, intersegment instrument collision detecting and adjusting, skip instruction label matching, skip instruction collision detecting and adjusting and skip instruction label rematching. By the assembler designing method based on the instruction set processor special for the very long instruction words, instruction-level parallelism of the assembler is improved, and application fields of the application specific instruction set process based on the very long instruction words are greatly expanded.

Description

technical field [0001] The invention belongs to the technical field of computer microprocessors, and further relates to a design method of a special-purpose instruction set processor assembler based on a super-long instruction word structure in a microprocessor assembler. The assembler designed by the method can not only complete The basic functions of the traditional assembler can also realize register renaming and instruction scheduling of the compiler part, and improve instruction-level parallelism. Background technique [0002] ASIP is a brand-new circuit design technology developed in application-specific integrated circuit and field programmable gate array technology. Its core idea is to develop a set of tailor-made special microprocessor instruction set and the microprocessor architecture that implements the instruction set for a certain type of application field. The use of special instruction set processor technology has the following advantages: the field programm...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
Inventor 张犁宋云朋李森李甫石光明李钦鹏
Owner XIDIAN UNIV
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