Instruction set encoding method based on embedded special instruction set processor

Abstract

The invention provides an instruction set encoding method based on an embedded special instruction set processor, comprising five steps of: defining machine code bit wide, defining instruction type, a defining addressing mode, a dividing instruction code filed and encoding. The instruction set is optimized according to the characteristic that both an internal memory and a data bus resource of a Field Programmable Gate Array (FPGA) take 18 bits as basic bit wide. The instruction set comprises 16 pieces of multifunctional instructions in the types of arithmetic and logic operation, data interchange and program sequencing, wherein the instructions comprise protective instruction fields required for constructing a single instruction stream-multiple data stream concurrent processing system with instruction independency capability. The instruction set disclosed by the invention has integral and simplified application models; under the two application models, the code length of an instruction machine can be respectively shortened to 16-bit and 14-bit so that the utilization efficiency of an internal circuit resource of the FPGA and the instruction execution speed of a processor are greatly improved.

Description

technical field [0001] The invention belongs to the technical field of computers, and further relates to an instruction set encoding method based on an embedded application-specific instruction set processor (ASIP) in a microprocessor instruction set. The instruction set defined by the method is based on a field programmable gate array (FPGA ) The internal memory and data bus resources are optimized with 18 bits as the basic bit width, which is suitable for FPGA embedded processing systems. Background technique [0002] Application Specific Instruction Set Processor (ASIP) technology is an emerging technology in the field of microprocessors. Its core idea is to develop a set of specialized microprocessor instruction sets and the microprocessor architecture that implements the instruction set according to specific application fields. ASIP is usually implemented in FPGA by means of embedding, which can make full use of the large circuit scale, rich on-chip resources and recon...

AI Technical Summary

Problems solved by technology

The disadvantages of this patent are: the machine code word length of the instruction set is too long, and there is only one application mode, and the corresponding processor architecture is difficult to run efficiently in the FPGA; one instruction can only complete one function, and there is no user Custom post-processing operations, the addressing mode of the operand is complex, which reduces the instruction execution speed; there is no Guarded Instruction control field, so it cannot be used to build a single instruction flow-multiple data flow with instruction autonomy ( SIMD) parallel processing system

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