Address generator for Turbo code and LDPC (Low Density Parity Check) code decoder

An address generator, LDPC code technology, applied in the direction of error correction/detection using block codes, error detection coding using multi-bit parity bits, machine execution devices, etc., which can solve the problem of limited flexibility and inability to decode Process control and other issues to achieve the effect of high flexibility

Inactive Publication Date: 2015-04-29
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Among the currently existing address generators, the ASIC design is mainly aimed at the turbo code address generator [5], which cannot control the decoding process through instructions, and is relatively limited in flexibility

Method used

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  • Address generator for Turbo code and LDPC (Low Density Parity Check) code decoder
  • Address generator for Turbo code and LDPC (Low Density Parity Check) code decoder
  • Address generator for Turbo code and LDPC (Low Density Parity Check) code decoder

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Embodiment Construction

[0021] The technical scheme of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0022] The address generator proposed by the present invention is used in multi-mode Turbo codes and LDPC code decoders, figure 1 It is the overall architecture diagram of multi-mode Turbo code and LDPC code decoder. The decoder is capable of error correction decoding of Turbo codes and LDPC codes. The input interface is responsible for various data inputs, including the initialization of the instruction / data memory of the control processor and the dedicated processor, the input of the channel LLR in the channel information storage unit, and the input of various error correction code information. The control processor is a RISC processor with a custom instruction set, responsible for monitoring the entire decoding process, calculating configuration information, configuring special processors, etc. The channel information storage unit is used...

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Abstract

The invention belongs to the technical field of special instruction set processors and particularly relates to an address generator for a Turbo code and LDPC (Low Density Parity Check) code decoder. The address generator can generate addresses for Turbo codes and LDPC codes in various wireless communication standards, including LTE / UMTS / WiMAX / WIFI (Long Term Evolution / Universal Mobile Telecommunications System / Worldwide Interoperability for Microwave Access / Wireless Fidelity) and the like. The address generator adopts a hybrid structure and mainly comprises an instruction memory, an instruction fetch module, a pre-coding module, a multimode address computation data path, a data memory and the like, wherein the multimode address computation data path can form different pipeline structures according to configuration information and execute address computation according to an instruction. Compared with the general address generator, the address generator has wider standard coverage, and can generate the addresses for the Turbo codes and the LDPC codes.

Description

technical field [0001] The invention relates to the technical field of special-purpose instruction set processors, in particular to an address generator for Turbo code and LDPC code decoders. Background technique [0002] Turbo code is a kind of error correction code with strong error correction performance, which is widely used in wireless communication. Relevant standards include Universal Mobile Telecommunications System (UMTS) [1], Long Term Evolution (LTE) [2], Worldwide Interoperability for Microwave Access (WiMAX) [3] [0003] LDPC code is a kind of error correction code widely used in wireless communication. Related standards include Worldwide Interoperability for Microwave Access (WiMAX) [3] and Wireless Local Area Network (WIFI) [4]. [0004] Among the currently existing address generators, the ASIC design [5] is mainly aimed at the Turbo code address generator, which cannot control the decoding process through instructions, and is relatively limited in flexibili...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11H03M13/27G06F9/30
Inventor 周晓方杨庆庆
Owner FUDAN UNIV
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