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Logic resource sharing method for special instruction set processor

A technology of logic resources and special instructions, applied in the field of logic resource sharing, can solve problems such as poor readability, maintainability, affecting system operating frequency, and increasing control complexity

Pending Publication Date: 2021-07-06
谷芯(广州)技术有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] (1) Only path-based resource sharing will introduce too many selector MUX, thereby increasing the control complexity and affecting the operating frequency of the system
[0006] (2) The integrity of the calculation mode of an instruction is broken, and the readability and maintainability of the design are poor

Method used

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  • Logic resource sharing method for special instruction set processor
  • Logic resource sharing method for special instruction set processor
  • Logic resource sharing method for special instruction set processor

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Embodiment Construction

[0031] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0032] Given the area constraint A of the extended functional unit eFU, the calculation mode set "=(S 1 , S 2 ,...,S k ), computing the optimal transformation set of the pattern set 「 Calculate the similarity matrix R of the pattern set "; and set:

[0033] 1) Gain δ(S 1 )≥δ(S 2 )≥…δ(S K-1 )≥δ(S k );

[0034] 2) Calculation mode set "and optimal transformation set The area resource consumed by each arithmetic logic operation included in the calculation mode is 1;

[0035] Then, the purpose of the present invention is in the optimal transformation set Find a way of grouping computing modes, so that the gain generated by the computing modes implemented on a given extended functional unit eFU achieves a local or global maximum.

[0036] Such as figure 2 and image 3 Shown, a kind of logic resource sharing method for spec...

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Abstract

The invention discloses a logical resource sharing method for a special instruction set processor. The method comprises steps of S1, an optimal transformation set being partitioned, and a similarity matrix R being partitioned according to columns; S2, for unshielded elements of each block, scanning the value of each element line by line from the first row and the first column, and searching the maximum element value gamma i, j appearing for the first time as a growth point for further expansion; S3, searching a maximum element value gamma i, a appearing for the first time in the ith row indicated by the coordinates (i, j) of the growing points, searching a maximum element value gamma j, b appearing for the first time in the jth row, and then shielding all element values in the ith row and the jth row; S4, judging the newly found element values gamma i, a and gamma j, b, and if all the elements are 0, continuing; otherwise, shielding or repeating the step; and S5, grouping and archiving the calculation modes generated in the step S4. The method has advantages of being simple in principle, easy to implement, capable of improving calculation efficiency and resource utilization rate and the like.

Description

technical field [0001] The invention mainly relates to the technical field of instruction set processors, in particular to a logical resource sharing method for special instruction set processors. Background technique [0002] Applications usually contain a large number of fixed computing patterns (Computing Pattern), such as figure 1 Butterfly operation in Fast Discrete Cosine Transform (FDCT). Solidifying these computing modes into dedicated extended instructions can significantly improve computing efficiency. The application-oriented instruction set processor (Application Specific Instruction-set Processor, ASIP) is to improve the performance of the processor in this way. Such as figure 1 As shown, in order to facilitate the design, a dedicated extended functional unit (extended Functional Unit, eFU) is usually designated in the ASIP to implement an extended instruction set (extended Instruction-Set Architecture, eISA). [0003] However, affected by factors such as ar...

Claims

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Application Information

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IPC IPC(8): G06F9/30
CPCG06F9/30003
Inventor 陈虎曹强辉
Owner 谷芯(广州)技术有限公司
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