Petri net model based ASIP (application specific instruction set processor) behavior logic synthesis method

A logic synthesis and model technology, applied in CAD circuit design, special data processing applications, instruments, etc., can solve problems such as verification, debugging difficulty, design difficulty and cycle increase.

Inactive Publication Date: 2018-02-13
JINLING INST OF TECH
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AI Technical Summary

Problems solved by technology

Due to directly facing the bottom-level signal timing, the design difficulty and cycle will increase for complex (multi-launch, out-of-order, correlation, etc.) and special (ASIP user-defined instructions) behaviors; the corresponding verification and debugging will also be more complex. Difficult, let alone optimized and scaled

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  • Petri net model based ASIP (application specific instruction set processor) behavior logic synthesis method
  • Petri net model based ASIP (application specific instruction set processor) behavior logic synthesis method
  • Petri net model based ASIP (application specific instruction set processor) behavior logic synthesis method

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Embodiment Construction

[0020] The pipeline behavior logic and its ADL description model are one of the key issues in processor design. The pipeline ADL description based on the Petri net model, namely PNML, is further obtained. After verification by third-party tools, it is synthesized into HDL and carried out in EDA and SoC environments. Architecture exploration and optimization.

[0021] In computer architecture, the position in the Petri net can be used to represent the local state of the system, such as queues, buffers, resources, etc.; transitions are used to describe events that cause system state changes, such as information processing, memory reading and writing, data processing, etc. Operations such as sending and receiving; arcs indicate the relationship between states and events, and the quantitative attributes can also be expressed by means of position capacity and arc weights, thus giving the pipeline behavior based on the Petri net model. The essence of a pipeline is a collection of co...

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Abstract

The invention relates to a design of a computer architecture, in particular to a design of an architecture for an application specific instruction set processor (ASIP). The method specially includes the steps of 1), establishing a Petri net based ASIP pipeline behavior model and adopting PNML (petri net markup language) to perform normative description; 2), achieving logic synthesis after the ASIPpipeline behavior model is mapped into a state machine view through organic relationship between a Petri net and a state machine; 3), downloading hard-link logic generated by an EDA tool chain to a real physical environment SoC for detection and running, and performing performance evaluation and optimizing the pipeline design. As a quite potential system level design method, the method has the advantages that normative Petri net model semantics and behaviors are acquired, correctness of the system's functionality can be verified in expectation, the method can serve as comprehensive tool inputand system technical documentation standards, and the executable description function of the method can be expanded through third-party tools.

Description

technical field [0001] The present invention relates to a design of a computer architecture, in particular to a design for an ASIP (Application Specific Instruction Set Processor, application specific instruction set processor) architecture. Background technique [0002] The pipeline is the core component of the processor, and its design and optimization are extremely complex. No implementation details are given beyond the basic principles of operation provided in the textbook. The existing pipeline design mainly adopts the traditional logic design method, and the design of its data channel and controller state machine depends on the experience of the designer; of course, the use of advanced EDA software can partially improve the design efficiency. [0003] In the existing design method, the timing combination of pipeline signals in a typical situation is defined as the corresponding state, which is realized by the timing logic of the state machine. Due to directly facing ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/327G06F2115/10
Inventor 朱勇
Owner JINLING INST OF TECH
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