Petri net model based ASIP (application specific instruction set processor) behavior logic synthesis method

Abstract

The invention relates to a design of a computer architecture, in particular to a design of an architecture for an application specific instruction set processor (ASIP). The method specially includes the steps of 1), establishing a Petri net based ASIP pipeline behavior model and adopting PNML (petri net markup language) to perform normative description; 2), achieving logic synthesis after the ASIPpipeline behavior model is mapped into a state machine view through organic relationship between a Petri net and a state machine; 3), downloading hard-link logic generated by an EDA tool chain to a real physical environment SoC for detection and running, and performing performance evaluation and optimizing the pipeline design. As a quite potential system level design method, the method has the advantages that normative Petri net model semantics and behaviors are acquired, correctness of the system's functionality can be verified in expectation, the method can serve as comprehensive tool inputand system technical documentation standards, and the executable description function of the method can be expanded through third-party tools.

Description

technical field [0001] The present invention relates to a design of a computer architecture, in particular to a design for an ASIP (Application Specific Instruction Set Processor, application specific instruction set processor) architecture. Background technique [0002] The pipeline is the core component of the processor, and its design and optimization are extremely complex. No implementation details are given beyond the basic principles of operation provided in the textbook. The existing pipeline design mainly adopts the traditional logic design method, and the design of its data channel and controller state machine depends on the experience of the designer; of course, the use of advanced EDA software can partially improve the design efficiency. [0003] In the existing design method, the timing combination of pipeline signals in a typical situation is defined as the corresponding state, which is realized by the timing logic of the state machine. Due to directly facing ...

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Problems solved by technology

Due to directly facing the bottom-level signal timing, the design difficulty and cycle will increase for complex (multi-launch, out-of-order, correlation, etc.) and special (ASIP user-defined instructions) behaviors; the corresponding verification and debugging will also be more complex. Difficult, let alone optimized and scaled

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