An extensible asip structure platform and instruction processing method

Abstract

The invention discloses an extensible ASIP structure platform and an instruction processing method. The platform is provided with an assembly line of instruction execution logic, the instruction execution logic comprises n clusters, the clusters 0-(n-2) are conventional clusters and used for achieving conventional instructions, and each cluster comprises two arithmetic logic units ALU and a 4-read-2-write distributed register file RF; the cluster n-1 is an extension cluster, is used for realizing a special extension instruction, and comprises an ERF (Extended Register Function) with 6 read ports, 2 write ports and at most 32 universal registers, an EFU (Extended Function Unit) with 6 inputs and 2 outputs, and an arithmetic logic unit ALU (Arithmetic Logic Unit); an outflow control networkunit ICN and an operand transfer network unit OPN are included between the clusters; and the execution management unit EMU coupled with each ALU or EFU and the register management unit RMU coupled with each RF or ERF form hardware of an instruction execution control mechanism. According to the method, instruction processing is completed based on the platform. The method has the advantages of beingeasy to implement, capable of improving the expansibility of the special instruction set processor and the like.

Description

technical field [0001] The invention mainly relates to the technical field of processors, in particular to an extensible ASIP structure platform and an instruction processing method, which can improve the extensibility of special instruction set processors. Background technique [0002] In a single-core processor, dividing resources into multiple clusters (Cluster) can eliminate or reduce constraints on the scalability of the processor by register file (Register File, RF) access ports and centrally controlled instruction outflow logic. Each cluster usually includes one or more functional units (Functional Unit), a register file, inter-cluster communication through shared storage (register file / cache, etc.) or crossbar (Crossbar). The program counter (PC) and decode logic can be shared by multiple banks or distributed in each bank. [0003] An application-oriented instruction set processor (Application Specific Instruction-setProcessor, ASIP) can effectively improve the perf...

AI Technical Summary

Problems solved by technology

However, due to the limitation of instruction word length (usually 16 / 32 / 64 bits) and instruction operands (usually no more than 3), the register resources available in clustered uniprocessors are very limited (usually 16 / 32 / 64 bits) 64), and cannot support dedicated extension instructions with more than 4 operands

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